Cross-Point Magnetic Junction Memory Array With Isolation Transistor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Magnetic junction memory arrays face challenges at higher memory cell densities due to increased switching fields and currents, leading to issues like cross-talk, power consumption, and writeability problems, as the switching field increases with smaller magnetic elements, requiring larger driving circuits and potentially switching neighboring cells.
Innovation Solution
A magnetic junction memory array with a cross-point architecture, where each memory cell includes a magnetic pinned layer between a magnetic bit and an isolation transistor, using a write head to apply a magnetic field for data writing and read circuitry to detect resistance changes for data retrieval, without requiring write circuitry, and an electrically conductive cover layer to protect the bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of magnetic memory cells is decreased to increase memory density, then memory density is improved, but coercivity increases requiring greater power and larger conductors
Solution Approach 1:
The patent segments the write operation from the read operation by using a separate write head for data writing while the memory array itself performs only read operations. This segmentation allows the memory cells to be optimized for low-power read operations while the write head handles the high-power switching function externally.
Solution Approach 2:
The patent introduces a write head as an intermediary component that applies magnetic fields to write data to the memory array without requiring high-power write circuitry within the memory cells themselves. The write head acts as an external mediator that performs the switching function.
2Quantity of substance
If the size of magnetic memory cells is decreased to increase memory density, then memory density is improved, but the switching field increases leading to cross-talk and inadvertent switching of neighboring cells
Solution Approach 1:
The patent extracts the write function from the memory cell structure itself and places it in a separate write head. This removes the source of cross-talk problems from the dense memory array, as the write head can be positioned and controlled to write to specific cells without affecting neighbors.
Solution Approach 2:
The write head serves as an intermediary that enables precise targeting of individual memory cells during write operations. By using magnetic field confinement and precise positioning of the write head, data can be written to selected cells without inadvertently switching neighboring cells.
3Ease of operation
If traditional write circuitry is used in each memory cell, then write capability is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent makes the memory array universal by enabling it to perform both read and write operations through different mechanisms. The same memory cell structure can be read using low-power electrical signals while write operations are performed externally by the write head, eliminating the need for separate write circuitry in each cell.
Solution Approach 2:
The memory array serves itself by using its own magnetic bits and resistance properties to store and indicate data states. The read circuitry uses the inherent magnetic resistance of the bits to detect stored data without requiring additional write circuitry, allowing the structure to be self-sufficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for efficient data writing and reading with reduced power consumption and minimized cross-talk, enabling reliable operation at higher densities by using a magnetic field to switch the magnetization orientation of the free layer, while the read circuitry accurately detects resistance changes without inadvertently switching neighboring cells.
Implementation Method 1
Data is written to a free layer of the magnetic junction by an external magnetic filed imposed by a write head
Implementation Method 2
the data is read out as either a high or low resistance of the magnetic junction
Data Source
AI summary
A magnetic junction memory array and methods of using the same are described. The magnetic junction memory array includes a plurality of electrically conductive word lines extending in a first direction, a plurality of electrically conductive bit lines extending in a second direction and forming a cross-point array with the plurality of electrically conductive word lines, and a memory cell proximate to, at least selected, cross-points forming a magnetic junction memory array. Each memory cell includes a magnetic pinned layer electrically between a magnetic bit and an isolation transistor. The isolation transistor has a current source and a gate. The current source is electrically coupled to the cross-point bit line and the gate is electrically coupled to the cross-point word line. An electrically conductive cover layer is disposed on and in electrical communication with the magnetic bits.