Magnetic Memory Burst Write with Mask Register
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Solution Overview
Problem
Magnetic random access memory (MRAM) and spin torque transfer MRAM (STTMRAM) suffer from slower write operations compared to static random access memory (SRAM), even in burst modes, where write operations typically require multiple clock cycles, hindering performance.
Innovation Solution
A memory device with a magnetic memory unit that performs burst write operations using a mask register to inhibit or enable data units, allowing for overlapping of write operations with the receipt of subsequent data units, thereby reducing the number of clock cycles required for a burst write and emulating a DRAM-like interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If burst write operations are performed in MRAM/STTMRAM, then data transfer capability is improved, but write operation speed remains slower compared to SRAM
Solution Approach 1:
The patent applies preliminary action by receiving and buffering the next burst of data before the current burst write operation is complete. The memory device allows the next burst data to be received and prepared in advance, so that when the current write operation finishes, the next data is already ready to be written immediately, eliminating idle time and improving overall write speed.
Solution Approach 2:
The patent implements continuity of useful action by overlapping the receive operation of one burst with the write operation of the previous burst. This pipelining approach ensures that the memory device is continuously productive - while one burst is being written, the next burst is being received and prepared, eliminating idle cycles and maintaining continuous useful action throughout the data transfer process.
2Reliability
If write operations require multiple clock cycles in MRAM/STTMRAM, then data integrity is ensured, but time consumption increases
Solution Approach 1:
The patent applies preliminary action by receiving and validating data in advance before the actual write operation completes. The data integrity checks and preparation are performed on the next burst while the current burst is being written, so that when writing occurs, the data is already verified and ready, maintaining reliability while reducing total time consumption.
Solution Approach 2:
The patent implements dynamics by creating an overlapping pipeline where data reception, validation, and write operations occur in dynamic succession rather than rigid sequence. The system dynamically manages multiple data bursts at different stages of processing simultaneously, optimizing the balance between ensuring data integrity through proper sequencing and minimizing total operation time through parallel processing stages.
Data Source
AI summary
A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array.