Magnetic Memory Cell With Dual Select Transistors
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Solution Overview
Problem
Magnetic memory cells face challenges in achieving high write speed while maintaining read stability due to high write and read currents, which can cause read errors if the read current exceeds the critical switching current of the magnetic tunnel junction (MTJ) element.
Innovation Solution
The implementation of a memory cell design that includes a cell selector unit with a first select transistor for write operations and a second select transistor for read operations, utilizing a low threshold voltage (LVT) transistor for writing and a high threshold voltage (HVT) or regular threshold voltage (RVT) transistor for reading, along with a back bias applied to the transistor body to control current levels, allowing for separate write and read paths and reducing read current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high write current is used to improve write speed, then write speed is improved, but read current increases causing read errors
Solution Approach 1:
The patent divides the single select transistor into two separate transistors: a first select transistor (ST1) dedicated to write operations and a second select transistor (ST2) dedicated to read operations. This segmentation allows independent optimization of each transistor's characteristics - ST1 can be designed for low threshold voltage to enable high write current, while ST2 can be designed for high threshold voltage to limit read current and prevent read errors.
Solution Approach 2:
The patent applies different threshold voltage characteristics to different transistors based on their specific functional requirements. The first select transistor uses low threshold voltage (LVT) characteristics optimized for write operations requiring high current, while the second select transistor uses high threshold voltage (HVT) characteristics optimized for read operations requiring current limitation. This local quality differentiation resolves the contradiction between write speed and read stability.
2Device complexity
If a single select transistor is used, then device complexity is reduced, but current control for separate write and read operations is insufficient
Solution Approach 1:
The single select transistor is segmented into two specialized transistors (ST1 for write, ST2 for read), each with independently optimized threshold voltages. This segmentation increases adaptability by enabling separate current control for write and read operations, while the overall device complexity remains manageable through systematic design.
Solution Approach 2:
The patent introduces dynamic control capability by enabling independent threshold voltage selection for different operational modes. The first select transistor dynamically enables high current flow during write operations, while the second select transistor dynamically limits current during read operations, providing adaptive current control based on operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances write speed and stability by increasing write current and reducing read current, thereby improving read operations and preventing read errors.
Implementation Method 1
A magnetic memory cell stores information by changing electrical resistance of a magnetic tunnel junction (MTJ) element. The MTJ element typically includes a fixed (pinned) magnetic layer and a free magnetic layer.
Implementation Method 2
Magnetic orientation of the free layer flips by a direction or an opposite direction of electric currents exceeding a critical select current.
Data Source
AI summary
Memory cells and methods of forming thereof are disclosed. The memory cell includes a substrate and first and second select transistors. The first select transistor serves as a write selector and the second select transistor serves as a read selector. The gate of first select transistor is coupled to a write wordline (WL_w) and the gate of the second select transistor is coupled to a read/write wordline (WL_r/w). The source regions of the first and second select transistors are coupled to a source line (SL). A body well is disposed in the substrate. The body well serves as a body of the first and second select transistors. A back bias is applied to the body of the select transistors. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled with a bitline (BL) and the first and the second select transistors.