Two-Element Magnetic Memory Cell Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Magnetic memory cells with single memory bits are prone to failure due to incorrect setting of reference elements or resistance changes over time, leading to improper data storage.
Innovation Solution
A magnetic memory cell comprising two magnetoresistive memory bits with a comparator to determine logical states based on equivalent resistance values, allowing for shared comparative logic among multiple cells, and using applied magnetic fields to change resistance values for writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single memory bit magnetic memory cells are used, then device complexity is reduced, but reliability deteriorates due to incorrect reference element setting or resistance changes over time
Solution Approach 1:
The patent merges two memory bits into a single memory cell, where the first and second memory bits work together to store one logical state. This combination allows the cell to compare resistance values between the two bits, making the storage reliable even if one bit's resistance changes over time or during manufacturing, thus resolving the reliability issue without requiring complex external reference elements.
Solution Approach 2:
The two memory bits in the cell serve multiple functions: they act as both storage elements and as mutual reference elements for comparison. Each bit can be used to determine the logical state by comparing its resistance with the other bit, eliminating the need for separate, precision-critical reference elements and reducing manufacturing complexity while improving reliability.
2Measurement precision
If reference elements are used for determining logical states, then measurement precision is improved, but manufacturing precision requirements increase due to incorrect setting during manufacturing
Solution Approach 1:
The memory bits serve themselves as reference elements. Instead of requiring externally manufactured and precisely set reference elements, each memory bit compares its resistance with another memory bit in the same cell. This self-referencing mechanism eliminates the need for high-precision manufacturing of separate reference elements, as the bits automatically provide their own reference for logical state determination.
3Reliability
If resistance changes over time are accounted for, then reliability is improved, but device complexity increases due to additional comparison logic
Solution Approach 1:
The same two memory bits used for storage also serve as the reference elements for comparison. When determining the logical state, the resistance of one bit is compared with the other bit in the pair. This dual-use approach allows the cell to compensate for resistance drift over time without adding separate reference elements or complex comparison circuits, as the storage bits themselves perform the reference function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures reliable data storage by accurately interpreting logical states through equivalent resistance comparisons and adaptable resistance changes, reducing errors caused by inherent variations and manufacturing inaccuracies.
Implementation Method 1
Two magnetoresistive memory bits are provided. The bits may be magnetic tunneling junction devices (MTJs). An applied magnetic field may be used to change a resistance value of the first bit and/or the second bit
Implementation Method 2
A comparator may be used to determine a logical state of the memory cell. The equivalent resistance value may include a range of resistances
Data Source
AI summary
A magnetic memory cell that includes at least two magnetoresistive memory bits is presented. The memory cell is capable of storing at least two logical states. The first logical state occurs when the bits share the same orientation, such as a parallel orientation or an antiparallel orientation. The second logical state occurs when the bits have opposite orientations. In the second logical state one of the bits has a parallel orientation and the other bit has an antiparallel orientation.