Magnetic Memory Interconnect Layout for Lower-Power High Integration
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Solution Overview
Problem
Current magnetic memory devices face challenges in achieving high integration and low power consumption while maintaining effective electrical characteristics, particularly in the design of magnetic tunnel junctions and interconnection structures.
Innovation Solution
The magnetic memory device incorporates a substrate with a cell region and peripheral circuit region, featuring a specific layered structure including etch stop layers, interlayer insulating layers, data storage structures, and interconnection structures with optimized dimensions and materials to enhance electrical characteristics, such as recessed top surfaces and protective insulating layers, and contact portions with controlled heights and spacings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interconnection structure uses conventional contact plug heights, then the manufacturing process is simpler, but the electrical characteristics and reliability are degraded due to stress and defects
Solution Approach 1:
The patent applies local quality by differentiating the contact portion height from the lower contact plug height. Specifically, the contact portions of the peripheral interconnection structure are configured to have a height less than that of the lower contact plugs, creating localized structural variation that optimizes electrical characteristics in the peripheral circuit region while maintaining overall device functionality.
Solution Approach 2:
The patent introduces dimensional variation by controlling the height dimension of contact portions relative to lower contact plugs. This height difference creates a stepped configuration that addresses stress distribution and electrical performance issues without requiring complete redesign of the entire interconnection system.
2Ease of manufacture
If the contact portions have the same height as lower contact plugs, then the manufacturing process is simpler, but stress concentration and manufacturing defects increase
Solution Approach 1:
The patent applies parameter changes by modifying the height parameter of contact portions. The contact portions are specifically designed to have a height less than that of the lower contact plugs, which changes the stress distribution profile and reduces manufacturing defects while maintaining ease of fabrication through standard process adjustments.
3Productivity
If the peripheral interconnection structure uses uniform contact plug heights, then the design is simpler, but electrical performance and power consumption are degraded
Solution Approach 1:
The patent implements local quality by creating distinct height levels for different interconnection components. The contact portions have a reduced height compared to lower contact plugs, which optimizes electrical performance in the peripheral circuit region and enables lower power consumption through improved current distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electrical characteristics of magnetic memory devices, enabling higher integration and lower power consumption, while minimizing defects in manufacturing and enhancing the reliability of interconnection structures.
Implementation Method 1
A resistance value of the magnetic tunnel junction pattern may be changed depending on magnetization directions of the two magnetic layers. For example, when the magnetization directions of the two magnetic layers are anti-parallel to each other, the magnetic tunnel junction pattern may have a relatively high resistance value. When the magnetization directions of the two magnetic layers are parallel to each other, the magnetic tunnel junction pattern may have a relatively low resistance value.
Data Source
AI summary
A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.