Magnetic Memory Device Intermediate Voltage Precharge
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Solution Overview
Problem
Conventional magnetic memory devices face inefficiencies in reading information due to high impedance states of read bit and word lines, leading to prolonged charging times and increased time required to switch between selected and non-selected states, especially as storage capacity increases and line thickness decreases.
Innovation Solution
The implementation of an intermediate voltage supply via resistors and diodes for read bit and word lines allows for rapid switching between selected and non-selected states by charging parasitic capacitance using a second power supply, reducing the time needed to switch read lines and enabling faster information retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of storage cells is increased to enhance storage capacity, then the storage capacity is improved, but the reading speed deteriorates due to increased resistance and parasitic capacitance of read lines
Solution Approach 1:
The patent applies preliminary action by pre-charging the parasitic capacitance of read bit lines and read word lines to an intermediate voltage level (e.g., Vcc/2) before actual reading operations. This is achieved through dedicated precharge circuits that activate before the selected read lines are needed, so when reading occurs, the lines are already in a favorable voltage state, reducing the time required for voltage transitions and enabling faster reading speed while maintaining high storage capacity
Solution Approach 2:
The patent segments the power supply system into multiple independent power supply circuits, each dedicated to specific read bit lines or read word lines. This segmentation allows different regions of the memory array to be charged independently and simultaneously, reducing the overall charging time for the entire array. The segmented approach enables parallel precharging operations, which maintains reading speed despite increased storage capacity
2Ease of operation
If the read lines are switched between selected and non-selected states, then information reading is enabled, but the switching time increases due to the need to charge and discharge parasitic capacitance
Solution Approach 1:
The patent uses preliminary action by pre-charging read lines to intermediate voltage levels before they are needed for reading operations. The precharge circuits activate in advance to set the voltage of non-selected read lines to Vcc/2, so when a line needs to be switched to a selected state, it already starts from a favorable voltage point rather than from ground or full voltage, significantly reducing the switching time
Solution Approach 2:
The patent introduces an intermediate voltage level (Vcc/2) as a mediator state for read lines. This intermediate voltage serves as a transition point that facilitates faster switching between selected and non-selected states. By using this intermediary voltage level, the patent reduces the voltage differential that needs to be traversed during switching, thereby reducing the time required for charge/discharge operations of parasitic capacitance
3Use of energy by moving object
If the read lines are kept in a high impedance state when not selected, then power consumption is reduced, but the time to charge the lines when selected increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the parasitic capacitance of read lines to an intermediate voltage level before the actual reading operation. This precharging is performed during periods when the lines are not actively being used for data transfer, so it does not significantly increase the average power consumption. However, when a read line needs to be activated, it is already in a favorable voltage state, reducing the charging time during the actual reading operation
Solution Approach 2:
The patent implements periodic action by alternating between precharge phases and active reading phases. During precharge phases, the parasitic capacitance of read lines is charged to intermediate voltage levels. During active reading phases, the lines are used for data transfer. This periodic cycling between precharge and active states allows the system to prepare lines in advance without continuously consuming high power, thus balancing power consumption and charging time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed reading of information from storage cells even with increased resistance and parasitic capacitance, as read lines can be switched quickly between states, thereby improving overall reading efficiency.
Implementation Method 1
The storage elements 1a and 1b include magnetoresistive effect revealing bodies 2a and 2b constructed using GMR (Giant Magneto-Resistive) or TMR (Tunneling Magneto-Resistive) effect
Data Source
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AI summary
A magnetic memory device (M) includes a plurality of storage cells (1) disposed in two dimensions, read lines (5a,5b) that supply a read current (Ib1,Ib2) for reading information from a first power supply (Vcc) to the respective storage cells, and a second power supply (51) that is connected to at least some of the read lines (5a,5b) and applies an intermediate voltage (Vry), which is lower than the voltage (Vcc) supplied by the first power supply, to the connected read lines (5a,5b).