Magnetic Memory ECC Layout Using Rank-Based Parity

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Solution Overview

Problem

Existing memory systems face challenges in efficiently correcting errors in data storage and retrieval, particularly in magnetic memory systems, due to the inherent instability of magnetization states and domain wall shifts, which can lead to data corruption.

Innovation Solution

A memory system with a magnetic memory and a memory controller that utilizes a first encoder to generate a first codeword with a first error correction code parity based on rank, ensuring that each bit string is written to a different magnetic body, and employs a combination of rank metric and Hamming distance-based error correction codes to correct errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If rank metric error correction code is used to correct multiple errors simultaneously, then error correction capability is improved, but calculation complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcalculation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the error correction process into two distinct stages: first applying rank metric-based error correction to handle multiple simultaneous errors, then applying Hamming distance-based error correction for remaining errors. This segmentation allows each correction method to specialize in specific error types, improving overall effectiveness while managing computational complexity through structured division of labor

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a dynamic, adaptive error correction approach that selectively applies different correction algorithms based on the specific error conditions detected. The system dynamically chooses to apply rank metric correction when multiple errors are detected, and Hamming correction for single errors, optimizing resource usage and calculation complexity based on actual error scenarios

Inventive Principle:
Principle #15Dynamics

2Reliability

If multiple error correction methods are combined, then error correction effectiveness is improved, but system complexity increases

Engineering Contradiction:
Improveerror correction effectivenessVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges two different error correction methodologies (rank metric and Hamming distance) into a unified error correction system. The combination leverages the strengths of both methods: rank metric for handling multiple simultaneous errors and Hamming distance for single error correction, achieving superior error correction effectiveness while maintaining manageable system complexity through integrated design

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an intermediary error detection and classification mechanism that determines which correction method to apply. This intermediary layer analyzes the error pattern and routes to the appropriate correction algorithm, effectively managing the complexity of having multiple correction methods while ensuring optimal error correction performance

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12493520B2Memory system generating error correction code parity based on rank
Publication Date: 2025.12.09 KIOXIA CORP
  • US12493520B2 patent drawing
  • US12493520B2 patent drawing
  • US12493520B2 patent drawing

AI summary

A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.