Magnetic Power Package Structure for Embedded Inductor Heat Dissipation
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Solution Overview
Problem
Traditional power management chip packages with embedded inductors suffer from poor heat dissipation, leading to chip damage or aging, and reduced service life due to the embedding of chips in substrates.
Innovation Solution
A package structure featuring a substrate with a winding, chip, and component electrically connected to it, encapsulated by a magnetic encapsulation layer containing soft magnetic metal powder for enhanced thermal conductivity and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip is embedded in the substrate to reduce package size, then the package size is reduced, but the heat dissipation performance deteriorates
Solution Approach 1:
The patent extracts the chip from the embedded configuration and places it in a suspended state above the substrate. This allows heat to dissipate more effectively from the chip surfaces that would otherwise be in contact with the substrate, directly resolving the heat dissipation problem while maintaining the compact package design.
Solution Approach 2:
The patent transitions from a planar embedded configuration to a three-dimensional suspended structure. By elevating the chip above the substrate using support posts and encapsulating it with molding compound, the design creates vertical heat dissipation pathways and increases surface area for thermal management without increasing the horizontal package footprint.
2Volume of moving object
If the chip is embedded in the substrate, then the package size is reduced, but the service life is reduced due to poor heat dissipation
Solution Approach 1:
By extracting the chip from the embedded configuration and suspending it above the substrate, the patent enables effective heat dissipation that prevents thermal aging and damage. This directly extends the service life of the chip while maintaining the reduced package size benefit.
3Volume of moving object
If the winding and chip are mounted separately on the substrate, then the package size is reduced, but the power management performance deteriorates due to larger distance between components
Solution Approach 1:
The patent combines the winding and chip into a closely integrated structure by suspending the chip directly above the winding assembly. This merging of components minimizes the distance between them, improving power management performance through reduced parasitic inductance and resistance while maintaining compact packaging.
Solution Approach 2:
By transitioning from separate planar mounting to a vertical three-dimensional arrangement, the patent reduces the horizontal distance between the winding and chip. The chip is positioned directly above the winding, creating a compact vertical stack that improves electrical performance while maintaining a small overall package footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The magnetic encapsulation layer provides strong thermal conductivity, allowing for effective heat dissipation from the chip, resulting in improved power management performance and reduced package costs.
Implementation Method 1
The magnetic encapsulation layer contains soft magnetic metal powder and has strong thermal conductivity. The magnetic encapsulation layer directly encapsulates the chip and can conduct heat well.
Data Source
AI summary
Disclosed are a package structure and a manufacturing method thereof. The package structure incudes: a substrate, having a first surface and a second surface; a winding, disposed on the first surface of the substrate, and electrically connected to the substrate; a chip, disposed on the first surface of the substrate, and electrically connected to the substrate; a component, disposed on the first surface of the substrate, and electrically connected to the substrate; and a magnetic encapsulation layer, disposed on the first surface of the substrate, and encapsulating the winding, the chip, and the component.