Magnetic Sensor Offset Cancellation via Subtractor Circuit
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Solution Overview
Problem
Conventional magnetic sensors using Hall elements face challenges in achieving high sampling rates and improving jitter characteristics, with issues such as residual offsets and insufficient gain in their output signals, particularly due to the need for adder circuits and limitations in offset cancellation.
Innovation Solution
The magnetic sensor design incorporates a magneto-electric transducer, switch circuit, amplifier circuit, subtractor circuit, and selector circuit to alternately apply bias voltages and perform subtraction processes, canceling offset voltages and enhancing sampling speed and jitter characteristics through phase reversal and filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an adder circuit is used to cancel offset voltages, then offset cancellation is achieved, but residual offset and insufficient gain occur in the final output signal
Solution Approach 1:
The patent inverts the conventional approach by using a subtractor circuit instead of an adder circuit to cancel offset voltages. The subtractor circuit subtracts the amplified output signal from the bias voltage, thereby eliminating the need for adder circuits and resolving the issues of residual offset and insufficient gain that occur with adder-based approaches.
Solution Approach 2:
The patent changes the operational parameter of the offset cancellation process by switching from addition to subtraction. This parameter change fundamentally alters how offset voltages are cancelled, transforming the conventional adder-based method into a subtractor-based method that eliminates residual offset and improves output signal accuracy.
2Measurement precision
If conventional offset cancellation methods are used, then offset voltages are cancelled, but sampling rate remains insufficient and jitter characteristics are poor
Solution Approach 1:
The patent implements continuous offset cancellation through a feedback mechanism where the subtractor circuit continuously adjusts the output signal by subtracting the amplified signal from the bias voltage. This continuous action enables high-speed sampling while maintaining precise offset cancellation, thereby improving both sampling rate and jitter characteristics.
Solution Approach 2:
The patent employs feedback by feeding the amplified output signal back to the subtractor circuit, which continuously adjusts the output based on the amplified signal. This feedback mechanism enables real-time offset cancellation at high sampling rates, improving both productivity and measurement precision simultaneously.
3Device complexity
If bias voltage is applied in a single direction, then circuit complexity is reduced, but offset cancellation and sampling performance are insufficient
Solution Approach 1:
The patent introduces dynamic bias voltage application by switching between multiple bias voltages (first bias voltage and second bias voltage) that are equal in magnitude but opposite in direction. This dynamic switching enables effective offset cancellation while maintaining relatively simple circuit configuration, resolving the contradiction between complexity and precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively cancels offset voltages and improves the sampling rate and jitter characteristics of magnetic field detection, reducing quantization noise and enabling stable magnetic field detection with increased precision.
Implementation Method 1
a magneto-electric transducer which generates an output voltage depending on a strength of a magnetic field
Data Source
AI summary
A magnetic sensor includes a magneto-electric transducer, a switch circuit, an amplifier circuit, a subtractor circuit, and a selector circuit. The subtractor circuit performs a first subtraction process of generating a first subtraction voltage by subtracting an amplification voltage obtained under an immediately prior first bias state from an amplification voltage obtained under a second bias state and a second subtraction process of generating a second subtraction voltage by subtracting an amplification voltage obtained under an immediately prior second bias state from an amplification voltage obtained under a first bias state in a serial and parallel manner. The selector circuit alternately selects the first subtraction voltage and the second subtraction voltage to output a select voltage.