Magnetoresistive Memory Integration in Logic-Embedded Semiconductor
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Solution Overview
Problem
The integration of memory and logic devices into a single semiconductor chip poses challenges in achieving compact, high-performance, and cost-effective designs, particularly in ensuring compatibility with various logic devices while maintaining the reliability and efficiency of memory functions.
Innovation Solution
A semiconductor apparatus is designed with a substrate having both logic and memory regions, featuring a magnetoresistive device-based memory system, where a variable resistance structure with a magnetoresistive device is integrated between insulating layers, allowing for efficient interconnection structures that maintain compatibility with logic devices and enhance memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory and logic devices are integrated into a single chip, then device complexity is reduced and cost is lowered, but compatibility with various logic devices becomes difficult to ensure
Solution Approach 1:
The magnetoresistive device is designed with a universal structure that can be integrated with different types of logic devices. The device uses standard interconnection structures (first and second interconnection structures passing through insulating layers) that are compatible with various logic device architectures, allowing the same memory cell structure to work with different logic technologies.
Solution Approach 2:
The semiconductor apparatus is divided into distinct logic region and memory region on the substrate, with separate insulating layers and interconnection structures for each region. This segmentation allows independent optimization of logic and memory functions while maintaining overall integration, resolving the conflict between reduced complexity and maintained compatibility.
2Ease of manufacture
If magnetoresistive device is integrated with logic devices, then manufacturing cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The magnetoresistive device is positioned in the vertical dimension within the base insulating layer, between the first and second insulating layers. The interconnection structures pass through the insulating layers in the vertical direction to connect to the magnetoresistive device. This three-dimensional arrangement reduces lateral alignment requirements compared to planar integration, easing manufacturing precision demands while maintaining cost effectiveness.
3Reliability
If variable resistance structure is added to the base insulating layer, then memory functionality is enhanced, but device complexity increases
Solution Approach 1:
The variable resistance structure (magnetoresistive device with lower and upper electrodes) is merged into the base insulating layer, combining the memory functional element with the interconnection insulation structure. The first and second interconnection structures pass through the first and second insulating layers to connect to the electrodes of the magnetoresistive device, creating an integrated structure that enhances memory functionality without adding separate complex interconnection layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a compact, high-performance embedded semiconductor apparatus with improved memory functionality, cost reduction, and design simplification, while ensuring compatibility with diverse logic devices and maintaining reliable circuit characteristics.
Implementation Method 1
a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure including a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked
Data Source
AI summary
A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.