Magnetoresistive Memory Device Vertical Stack RC Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Magnetoresistive memory devices face challenges in miniaturization due to increased resistance values and RC products of bit lines and source lines, leading to reduced operation speed and integration efficiency.
Innovation Solution
The use of a bit plate and source plate configuration with MTJ elements and double-gate transistors, allowing for conductors with a small RC product and enabling high-speed operation, even in small dimensions, by selecting only one MTJ element between the plates and forming transistors on a monocrystalline semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If bit lines and source lines are used in magnetoresistive memory devices, then data storage and retrieval are enabled, but resistance values and RC products increase during miniaturization, leading to reduced operation speed
Solution Approach 1:
The patent transitions from planar bit line/source line configuration to a vertical stacked configuration where MTJ elements are arranged in layers between bit plates and source plates. This dimensional change allows current to flow vertically through the stack, reducing the horizontal conductor length and thus the RC product, while enabling higher integration density.
Solution Approach 2:
The patent merges multiple functions into the vertical stack structure: the bit plate and source plate serve as both current paths and selection mechanisms, while the MTJ element integrates memory storage and switching functionality. This consolidation eliminates the need for separate long bit lines and source lines, reducing resistance and RC products.
2Quantity of substance
If bit lines and source lines are miniaturized to increase integration density, then device size is reduced, but resistance values increase, leading to higher RC products and slower operation
Solution Approach 1:
By stacking MTJ elements vertically between bit plates and source plates, the invention achieves high integration density without increasing the lateral footprint. The vertical current path maintains low resistance despite miniaturization, as the conductor length in the critical current path is minimized compared to planar configurations.
Solution Approach 2:
The invention changes the geometric parameters of the conductor configuration from long planar traces to short vertical stacks. This parameter change reduces both resistance and capacitance in the current path, maintaining low RC products even as device density increases through vertical stacking.
3Ease of manufacture
If conventional transistor configurations are used with MTJ elements, then circuit functionality is achieved, but manufacturing complexity increases and integration efficiency decreases
Solution Approach 1:
The patent combines the transistor gate control mechanism with the vertical stack structure, where the transistor is positioned to control current flow into the stack. This integration simplifies the overall circuit configuration by eliminating separate select line routing and reducing the number of discrete components needed for each memory cell.
Solution Approach 2:
The vertical stack structure serves multiple functions simultaneously: it provides the memory storage element (MTJ), the current path for read/write operations, and the selection mechanism through the transistor gate. This multi-functionality reduces circuit complexity compared to conventional configurations where each function requires separate dedicated structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration suppresses the increase in RC products during miniaturization, enabling high-speed operation and improved integration density while maintaining low resistance in the current path, and allows for a simpler manufacturing process.
Implementation Method 1
A memory device that stores data using a magnetoresistive effect is known
Data Source
AI summary
A memory device includes first and second resistance change elements and first and second double-gate transistors. The first resistance change element includes first and second terminals. The second resistance change element includes a third terminal coupled to the first terminal and a fourth terminal. The first double-gate transistor includes a fifth terminal coupled to the second terminal, a sixth terminal, and a first gate coupled to a first word line and a second gate coupled to a second word line. The second double-gate transistor includes a seventh terminal coupled to the fourth terminal, an eighth element, and a third gate coupled to the first word line and a fourth gate coupled to a third word line.