Main Memory Hardware Accelerator Shared Storage

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Solution Overview

Problem

Existing hardware accelerators face inefficiencies due to separate memory spaces and the need for data replication, leading to increased delay times and memory resource wastage during operation.

Innovation Solution

Implementing a main memory system where a hardware accelerator shares storage space with the host processor, utilizing a conversion manager to secure and access physical addresses directly from virtual addresses, eliminating the need for redundant data replication and reducing memory overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transferred from main memory to accelerator memory via DMA, then the accelerator can perform hardware acceleration, but the overhead for data transfer becomes too large when the amount of data is large

Engineering Contradiction:

Improvehardware acceleration performanceVSAvoiddata transfer overhead

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent merges the accelerator memory with the main memory to form a unified memory space, eliminating the need for separate DMA transfers between distinct memory spaces. The accelerator can directly access data within the shared main memory, thereby removing the data transfer overhead while maintaining hardware acceleration capabilities.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If separate memory spaces are used for host processor and accelerator, then each has dedicated access, but memory space is wasted due to data replication

Engineering Contradiction:

Improvededicated memory accessVSAvoidmemory resource wastage

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The patent combines the host processor memory space and accelerator memory space into a single shared main memory. This unified memory space allows both the host processor and accelerator to access the same data without replication, eliminating memory resource wastage while maintaining reliable dedicated access through address translation mechanisms.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If the accelerator uses virtual address translation through TLB, then virtual memory can be used, but the accelerator cannot access the TLB directly and must use physical addresses

Engineering Contradiction:

Improvevirtual memory supportVSAvoidaddress translation complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a conversion manager as an intermediary component that handles address translation between virtual and physical addresses. The conversion manager translates virtual addresses to physical addresses and provides them to the accelerator, enabling the accelerator to use virtual addresses indirectly while maintaining the benefits of virtual memory without requiring direct TLB access.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10565131B2Main memory including hardware accelerator and method of operating the same

Publication Date: 2020.02.18 IND ACADEMIC COOP FOUND YONSEI UNIV

AI summary

Disclosed is a main memory capable of speeding up a hardware accelerator and saving memory space. The main memory according to the present disclosure is at least temporarily implemented by a computer and includes a memory, and an accelerator responsible for performing an operation for hardware acceleration while sharing the storage space of a host processor and the memory.