Main Memory Bus Interfacing for Co-Processor I/O Bottlenecks

The patent applies universality by enabling the main memory bus to serve dual functions: its traditional role in connecting CPU to memory, and a new role in interfacing co-processors and I/O devices. The memory controller is enhanced to handle both memory operations and CPIO device communications through the same bus infrastructure, eliminating the need for separate I/O bus connections and thereby improving I/O performance while reducing overall system complexity.

The patent introduces the main memory bus as an intermediary between high-speed CPIO devices and the CPU. Instead of direct I/O bus connections that create bottlenecks, data from fast co-processors and I/O devices is routed through the high-bandwidth memory bus, which acts as a mediator capable of handling higher data rates. This resolves the bottleneck problem by providing a communication path that matches the speed capabilities of modern CPIO devices.

The patent merges the I/O communication path with the memory bus infrastructure. Co-processors and I/O devices are integrated into the memory subsystem architecture, allowing them to share the high-bandwidth memory bus with memory operations. This combining of previously separate pathways (memory bus and I/O bus) into a unified high-speed interface increases available data bandwidth while maintaining device functionality through the memory controller's ability to manage multiple device types.