Main Memory Prefetch Intelligence for Dependent Load Stall Reduction

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Solution Overview

Problem

Traditional dependent load operations in computing systems experience significant time delays due to the completion of the initial load instruction before the dependent load can begin execution, leading to software thread stalls.

Innovation Solution

Integration of prefetch intelligence into the main memory control function allows the dependent load instruction to start execution earlier by using a prefetch instruction that can begin execution once a cache miss is confirmed, with meta-data indicating the dependent load's address is calculated from the initial load's result, enabling simultaneous data retrieval from main memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional dependent load operations are used, then execution correctness is maintained, but stall time increases significantly

Engineering Contradiction:

Improvestall timeVSAvoidmemory control function complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by implementing a prefetch mechanism that speculatively executes dependent load instructions before the initial load completes. The memory control function predicts future memory access patterns and pre-fetches data into a buffer, allowing dependent loads to proceed without waiting for the initial load to finish, thus reducing stall time while maintaining correctness through validation logic.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If prefetch intelligence is integrated into main memory control function, then main memory accessing performance is improved, but device complexity increases

Engineering Contradiction:

Improvemain memory accessing performanceVSAvoidmemory control function complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the memory control function into distinct modular components: a prefetch engine that identifies and issues prefetch requests, a buffer structure that stores pre-fetched data, and a validation mechanism that ensures prefetch correctness. This modular architecture improves memory accessing performance through parallel operations while managing complexity through clear separation of concerns.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary buffer structure between the main memory and the processing units. This buffer acts as a mediator that holds pre-fetched data, allowing the memory control function to decouple the timing of memory accesses from instruction execution. The intermediary buffer enables performance improvement by providing data to dependent loads before the initial load completes, while the complexity is contained within the buffer management logic.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10977036B2Main memory control function with prefetch intelligence

Publication Date: 2021.04.13 INTEL CORP

AI summary

An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.