External Main Terminal Layout for Insulated Overlapping Lead Frames

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Solution Overview

Problem

Existing semiconductor devices face challenges in efficiently integrating collector and emitter electrode joint portions and lead frames due to overlapping configurations, which can lead to electrical interference and reduced efficiency.

Innovation Solution

The semiconductor device incorporates a design with a first and second main terminal formed in an integral manner, featuring planar trapezoidal lead frames with oblique or vertical substrate connections, allowing for a predetermined gap between them, enhancing electrical insulation and reducing interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If lead frames are arranged in overlapping configurations to integrate collector and emitter electrode joint portions, then device integration is improved, but electrical interference and reduced efficiency occur

Engineering Contradiction:
Improveintegration of electrode joint portionsVSAvoidelectrical interference
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The lead frames are segmented into distinct first and second lead frames with separate substrate connection portions. The first substrate connection portion connects to a first electrode joint portion while the second substrate connection portion connects to a second electrode joint portion, physically separating the electrical pathways to eliminate interference while maintaining integration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar overlapping lead frame arrangements to a three-dimensional configuration where lead frames are positioned at different heights above the substrate. The first lead frame is positioned at a first height and the second lead frame at a second height, using vertical spacing to prevent electrical interference while achieving integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If lead frames are positioned close together for compact design, then space utilization is improved, but electrical insulation deteriorates

Engineering Contradiction:
Improvespace utilizationVSAvoidelectrical insulation
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent employs vertical positioning to achieve electrical insulation while maintaining compact horizontal footprint. Lead frames are arranged at different heights (first height and second height) above the substrate, creating three-dimensional spacing that provides adequate insulation distance without increasing planar area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The substrate serves as an intermediary insulating layer between the first and second electrode joint portions. The substrate connection portions are positioned at different locations on the substrate, using the substrate material itself as the insulating medium that separates the electrical pathways while allowing compact integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250279339A1Semiconductor device and external connection main terminal
Publication Date: 2025.09.04 FUJI ELECTRIC CO LTD
  • US20250279339A1 patent drawing
  • US20250279339A1 patent drawing
  • US20250279339A1 patent drawing

AI summary

An external connection main terminal includes a P main terminal and an N main terminal. The P main terminal includes an external terminal, a horizontal portion of a planar trapezoidal shape parallel to an insulated circuit substrate, and a connection terminal extending obliquely or vertically from the horizontal portion toward the insulated circuit substrate. The N main terminal includes an external terminal, a horizontal portion of a planar trapezoidal shape parallel to the insulated circuit substrate and being located over the horizontal portion of the P main terminal so that the horizontal portions of the P and N main terminals are superimposed over each other with a predetermined gap between in a direction orthogonal to the insulated circuit substrate, and a connection terminal extending obliquely or vertically from the horizontal portion toward the insulated circuit substrate.