Mainboard Logic Startup Sequencing to Prevent Chip Power Peaks
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Solution Overview
Problem
The simultaneous startup of multiple logics in electronic chips leads to power peak states, causing noise signals and erroneous functioning due to instantaneous voltage changes, which existing technologies fail to adequately address.
Innovation Solution
A mainboard and electronic component with control units that manage the startup of logics at different times using control signals, preventing simultaneous initiation and thus reducing noise and ensuring normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple logics are started simultaneously in a chip, then the chip can function with all logics operating, but noise signals are generated due to power peak state causing erroneous functioning
Solution Approach 1:
The patent segments the startup process of multiple logics by dividing them into different groups that are activated at different time points. Instead of initiating all logics simultaneously, the control unit staggers their activation, thereby segmenting the power consumption profile and avoiding the power peak state that generates noise signals.
Solution Approach 2:
The patent applies preliminary action by preparing and controlling the startup sequence of logics in advance. The control unit pre-establishes a staged activation schedule where logics are brought online progressively rather than all at once, allowing the system to avoid simultaneous power demands and the resulting noise generation.
2Ease of operation
If different bias voltages are provided to initiate logics, then the logics can be initialized, but instantaneous voltage changes occur resulting in erroneous functioning
Solution Approach 1:
The patent segments the voltage application process by providing different bias voltages to different logic groups at different time points. This temporal segmentation prevents simultaneous voltage transitions across all logics, thereby avoiding instantaneous voltage changes that would cause erroneous functioning.
Solution Approach 2:
The control unit pre-establishes a voltage application sequence where bias voltages are applied progressively to different logic groups. This preliminary planning of voltage transitions ensures that voltage changes are staggered rather than simultaneous, maintaining reliability during initialization.
3Productivity
If all logics operate synchronously, then the chip functions with coordinated operation, but power consumption rises abruptly creating a power peak state
Solution Approach 1:
The patent segments the operation timeline by dividing logic activation into multiple phases. Instead of all logics starting and operating simultaneously causing an abrupt power rise, the control unit staggers their activation, creating a segmented power consumption profile that avoids power peaks while maintaining overall productivity.
Solution Approach 2:
The patent implements periodic action by activating logic groups in sequential periods rather than all at once. The control unit establishes a periodic startup schedule where different logic groups are brought online in successive time periods, transforming the abrupt power consumption into a more gradual, periodic pattern that avoids power peaks.
Data Source
AI summary
A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a control signal to the chip, controlling at least one of the logics based on the control signal at a first timing, and controlling at least another one of the logics based on the control signal at a second timing. The control signal is intent to substantially control actions of the logics synchronously. Moreover, a mainboard and an electronic component, utilizing the controlling method of logic operations, are provided.