Majority Gate ATPG for Test Compression
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Solution Overview
Problem
Current automatic test pattern generation (ATPG) techniques for integrated circuits require a large number of test patterns to achieve high fault coverage, leading to increased storage and processing demands, and existing compression methods do not adequately reduce the number of care bits needed for testing, which limits their effectiveness and efficiency.
Innovation Solution
The method identifies and utilizes majority gates within the integrated circuit design to simulate and confirm candidate majority gates, modifying ATPG to sensitize faults through these gates, thereby reducing the number of care bits required for testing and improving compression efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deterministic ATPG is used to generate test patterns, then fault coverage approaches 100%, but storage area in test-application equipment increases significantly
Solution Approach 1:
The patent extracts and identifies specific majority gate structures within the circuit design, separating them from the general logic network. By focusing ATPG efforts specifically on these identified majority gates rather than treating all circuit elements uniformly, the method reduces the overall number of test patterns needed while maintaining high fault coverage for the extracted critical structures.
Solution Approach 2:
The patent performs preliminary identification and classification of majority gates before the actual ATPG process. This preliminary action involves analyzing the circuit netlist to locate and mark majority gate structures, which then guides the subsequent test pattern generation to prioritize these areas, reducing the total patterns required.
2Quantity of substance
If the number of test patterns is reduced, then storage area decreases, but fault coverage may be compromised
Solution Approach 1:
The patent applies local quality by treating majority gate regions differently from the rest of the circuit. Instead of uniform testing approaches, the method concentrates testing resources on the identified majority gate locations where faults are most critical, using targeted test patterns that specifically address these local structures while reducing overall pattern count.
3Reliability
If scan chains are used for testing, then fault detection capability improves, but test application time increases due to loading requirements
Solution Approach 1:
The patent applies partial action by not requiring complete exhaustion of all possible scan chain patterns. Instead, it generates a reduced set of test patterns specifically tailored to detect faults in majority gates, achieving sufficient fault detection capability without the time penalty of applying all possible patterns to full scan chains.
Data Source
AI summary
A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.