Majority-Inverter Logic Synthesis for Lower-Area Digital Circuits
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Solution Overview
Problem
Current logic synthesis tools for digital integrated circuits are limited in further optimizing Boolean functions, particularly in reducing area, delay, and power consumption, despite advancements in data structures and algorithms.
Innovation Solution
The method employs Majority-Inverter Graphs (MIGs) with a novel Boolean algebra based on majority and inverter operations, utilizing transformations like commutativity, associativity, distributivity, and substitution to optimize logic circuits, reducing area, delay, and power consumption through reshaping, elimination, and substitution procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional logic synthesis tools use conventional Boolean operations (INV, AND, OR, MUX) for optimization, then they can handle large circuits and produce good results, but they cannot further reduce area, delay, and power consumption
Solution Approach 1:
The patent changes the fundamental parameters of Boolean algebra by introducing majority operators (returning the value assumed by more than half of the variables) and complementation operators as basis operations, replacing traditional INV, AND, OR, MUX operations. This parameter change in the operational basis enables further optimization of area, delay, and power consumption that was not achievable with conventional Boolean operations
Solution Approach 2:
The patent inverts the traditional approach by using majority operators and complementation as the primary basis operations, rather than using INV, AND, OR, MUX as conventions. This inversion of the operational foundation allows for novel optimization techniques including majority transformations, associativity transformations, distributivity transformations, and inverter propagation transformations that can further reduce circuit metrics
2Area of stationary object
If more transformation operations are applied to optimize logic circuits, then area reduction is achieved, but the complexity of the optimization process increases
Solution Approach 1:
The patent segments the optimization process into distinct transformation categories: majority transformations (Ω.M), associativity transformations (Ω.A), distributivity transformations (Ω.D), inverter propagation transformations (Ω.I), relevance transformations (Ψ.R), complementary associativity transformations (Ψ.C), and substitution transformations (Ψ.S). Each transformation type addresses specific optimization opportunities, allowing systematic reduction of logic circuit area while managing process complexity through structured segmentation
Solution Approach 2:
The patent introduces Majority-Inverter Graphs (MIGs) as an intermediary data structure that represents Boolean functions using majority operators and complementation. This intermediary representation enables the application of multiple transformation operations while maintaining a unified framework, facilitating area reduction through reshaping, elimination, and substitution procedures without overwhelming complexity
3Productivity
If conventional Boolean algebra operations are used for logic synthesis, then implementation is straightforward, but further performance improvement is limited
Solution Approach 1:
The patent creates a universal framework using Majority-Inverter Graphs that can represent and optimize any Boolean function. The MIG structure with majority operators and complementation serves as a multi-functional basis that enables simultaneous optimization of area, delay, and power consumption through various transformation operations, providing universal applicability while achieving superior performance improvement over conventional methods
Data Source
AI summary
A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ′. The method further comprises providing a commutativity, a majority (Ω.M), an associativity (Ω.A), a distributivity (Ω.D), an inverter propagation (Ω.I), a relevance (Ψ.R), a complementary associativity (Ψ.C), and a substitution (Ψ.S) transformation; and combining the Ω.M, Ω.C, Ω.A, Ω.D, Ω.I, Ψ.R, Ψ.C and Ψ.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the Ω.A, Ω.C, Ω.D, Ω.I, Ψ.R, Ψ.S and Ψ.C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the Ω.M transformation, applied left-to-right, and the Ω.D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iteration of steps (i) and (ii) till a reduction in area is achieved.