Majority Logic Sequential Latch With Non-Linear Polar Capacitors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Sequential circuits face challenges in reducing power consumption due to the dynamic power consumption associated with toggling transistors and extensive interconnects, which hinders the goal of lower power consumption in processors.
Innovation Solution
The use of non-linear polar capacitors in sequential circuits, such as 3-input majority gates and threshold gates, which eliminate the need for switching transistors and reduce interconnects, allowing for lower power operation and non-volatility, enabling processors to enter low power states without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional sequential circuits use switching transistors and interconnects, then the circuit can perform sequential logic operations, but the dynamic power consumption increases
Solution Approach 1:
The patent extracts and eliminates the switching transistor components from the sequential circuit, replacing them with a non-linear polar capacitor that inherently provides both storage and switching functionality. This extraction of unnecessary components directly reduces dynamic power consumption while maintaining the essential sequential logic operations.
Solution Approach 2:
The non-linear polar capacitor is designed to perform multiple functions simultaneously: it acts as both the storage element and the switching element in the sequential circuit. This multi-functionality eliminates the need for separate switching transistors and interconnects, thereby reducing power consumption while maintaining circuit capability.
2Use of energy by moving object
If processors operate at lower voltages to save battery power, then power consumption decreases, but data integrity may be compromised during low power states
Solution Approach 1:
The patent utilizes the unique parameter characteristics of non-linear polar capacitors, specifically their ability to maintain stable voltage thresholds across varying operating conditions. This allows the circuit to reliably maintain data integrity even when operating at lower voltages, as the capacitor's non-linear characteristics provide inherent noise margins and stability.
3Ease of operation
If sequential circuits use extensive interconnects to connect gates and transistors, then the circuit can be fully functional, but the power consumption and circuit area increase
Solution Approach 1:
The patent merges the storage function and switching function into a single non-linear polar capacitor component, eliminating the need for separate gates, transistors, and extensive interconnects. This consolidation maintains full sequential logic functionality while dramatically reducing the circuit area and associated power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction in power consumption, allowing processors to operate at lower voltages, achieve compact circuit designs, and maintain data integrity during low power states, with the non-linear polar capacitors providing intermittent operation and zero power drain when not in use.
Implementation Method 1
a first capacitor having a non-linear polar material and coupled to a first terminal of the ferroelectric capacitor
Implementation Method 2
a second capacitor coupled to a second terminal of the ferroelectric capacitor, wherein the second capacitor comprises ferroelectric material
Data Source
AI summary
A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.