Majority Voter Circuit Using Bit Omission for Noise-Robust Selection
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Solution Overview
Problem
Conventional semiconductor devices face challenges in impedance matching at high speeds, leading to data distortion and noise due to mismatched impedance, which affects the accuracy of majority voter circuits used in data bus inversion and low weight coding.
Innovation Solution
A majority voter circuit design that omits one or more bits from the data and inverted data to generate a voltage difference, allowing for the comparison of an odd number of bits to determine the majority, thereby reducing noise and data distortion, and includes an amplifying circuit to detect and amplify this voltage difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor devices operate at high speeds, then data transmission speed is improved, but impedance mismatch causes reflected waves and data distortion
Solution Approach 1:
The patent changes the parameter of data representation from standard binary to gray code, where only one bit changes between consecutive values. This parameter change in encoding methodology prevents simultaneous switching of multiple bits, thereby reducing signal reflection and impedance mismatch effects while maintaining high transmission speeds and improving data integrity
2Reliability
If OCD and ODT use differential signal to suppress noise, then signal integrity is improved, but the number of terminals required doubles
Solution Approach 1:
The patent uses gray code encoding where each data value is represented by a unique bit pattern that differs from adjacent values by only one bit. This copying approach with modified encoding reduces the effective number of simultaneous signal transitions needed, thereby reducing terminal requirements while maintaining signal integrity through reduced electromagnetic interference
3Productivity
If low weight coding is performed to reduce noise, then bandwidth is improved, but majority voter circuit accuracy deteriorates when equal numbers of 0s and 1s occur
Solution Approach 1:
The patent introduces asymmetric weighting in the majority voter circuit where bits are assigned different weights based on their position and significance. When equal numbers of 0s and 1s occur, the asymmetric weighting scheme provides a tie-breaking mechanism that maintains determination accuracy. This asymmetric approach preserves the bandwidth benefits of low weight coding while resolving the ambiguity in edge cases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the robustness of the majority voter circuit, reducing malfunctions caused by noise and impedance mismatch, improving data integrity and bandwidth by maintaining accurate majority determination even when the number of bits having a value of '0' equals the number of bits having a value of '1'.
Implementation Method 1
The amplifying circuit may be configured to detect and amplify the voltage difference between the first node and the second node
Data Source
AI summary
A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.