Managed Memory Error Protection With End-to-End CRC Checks
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Solution Overview
Problem
Existing memory systems fail to detect errors or faults within the memory device itself, leading to potential data corruption, which is critical in safety-critical systems like vehicle safety systems and autonomous vehicles.
Innovation Solution
Implementing an end-to-end cyclic redundancy check (CRC) with parity bits and check codes to detect and correct errors in data units within the memory system, using a memory system controller to generate and process protocol units and codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction mechanisms are implemented in memory systems, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error protection mechanism into distinct components: CRC calculation units positioned at both ends of the data path, separate parity bit generation and verification modules, and distributed check code storage across memory blocks. This segmentation allows error detection and correction functionality to be added without requiring complete system redesign, thus improving reliability while managing complexity through modular architecture.
Solution Approach 2:
The patent implements preliminary error detection by calculating CRC check codes and generating parity bits before data is written to memory. These error protection mechanisms are prepared in advance and stored alongside the data, enabling immediate error detection upon reading without requiring complex real-time analysis during data access operations.
2Reliability
If CRC check codes and parity bits are stored with data, then error detection capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the error protection data (CRC check codes and parity bits) with the actual user data by storing them in the same memory blocks and transmitting them through the same data path. This combining approach allows the memory system to utilize existing manufacturing precision capabilities without requiring separate high-precision storage channels, while still achieving robust error detection through the integrated error protection mechanisms.
3Reliability
If end-to-end error protection is implemented across the data path, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent performs error protection operations in advance by calculating CRC check codes and generating parity bits during the data writing phase. These computations are completed before data storage, so that when data is read, error detection can occur rapidly by simply verifying the pre-computed check codes against the stored data, minimizing additional processing time during critical data access operations.
Solution Approach 2:
The patent introduces CRC check codes and parity bits as intermediary elements that mediate between the data path endpoints. These intermediaries enable error detection without requiring direct complex verification between the memory controller and memory device, as the check codes serve as intermediate verification data that can be quickly computed and compared, reducing the time overhead of error protection.
Data Source
AI summary
Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.