Managed Memory Error Detection Across Internal Data Paths
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Solution Overview
Problem
Memory systems often fail to detect internal errors or faults, leading to potential data corruption, especially in safety-critical systems like vehicle safety systems, where errors in data paths within the memory device may go undetected.
Innovation Solution
A memory system configured to detect errors using end-to-end cyclic redundancy checks (CRC) and parity bits, where a controller generates and processes protocol units to identify errors from data received from a host device to data stored in memory devices, ensuring error detection and correction across the data path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection mechanisms (CRC, parity bits) are implemented in the memory system, then data integrity and reliability are improved, but device complexity increases
Solution Approach 1:
The error detection function is segmented into modular components: CRC calculation units positioned at the host interface, parity bit generation units at the memory interface, and corresponding verification units. This segmentation allows error detection to be implemented as discrete, manageable modules rather than a monolithic complex system, reducing overall system complexity while maintaining reliability.
Solution Approach 2:
CRC and parity bits act as intermediary elements that mediate between the host system and memory device. These check codes are generated as separate data structures that accompany the main data payload, allowing error detection without requiring fundamental changes to the core memory architecture or data paths.
2Reliability
If end-to-end error detection is implemented across the data path, then internal errors are detected, but processing time increases
Solution Approach 1:
Error detection codes (CRC and parity bits) are generated in advance during the data writing process and stored alongside the main data payload in the memory device. When data is read, the verification process uses these pre-generated codes immediately, eliminating the need for time-consuming re-calculation or extended verification procedures, thus minimizing processing time overhead.
Data Source
AI summary
Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.