Managed NAND Translation Using Host-Side Physical Address Mapping
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Solution Overview
Problem
Existing memory systems face inefficiencies in managing NAND translation, particularly in embedded memory systems, where host systems with larger storage capacity struggle to perform translation operations quickly, and embedded memory systems lack efficient management capabilities.
Innovation Solution
Implementing a host system that performs logical to physical address translations using the MFTL eMMC protocol, reducing the need for SRAM in the memory system controller and enabling faster translation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host system performs logical to physical address translations, then translation efficiency is improved, but the host system's storage capacity is underutilized
Solution Approach 1:
The host system is designed to perform multiple functions: it serves as both the storage management controller and the address translation engine. By integrating the translation function into the host system's existing control capabilities, the patent enables the host to efficiently manage NAND flash memory without requiring dedicated translation hardware, thus improving translation efficiency while utilizing the host's computational resources
2Adaptability or versatility
If embedded memory systems with controllers perform translation operations, then translation capability is provided, but additional resources are required
Solution Approach 1:
The translation function is extracted from the embedded memory system controller and relocated to the host system. This extraction eliminates the need for the embedded controller to have additional translation resources, reducing device complexity and resource requirements in the embedded system while maintaining full translation capability through the host system
Solution Approach 2:
The host system acts as an intermediary between the embedded memory system and the NAND flash storage. It receives high-level commands from the embedded system, performs the complex address translation operations, and manages the physical storage operations, thereby providing translation capability without requiring the embedded controller to directly handle translation resources
3Productivity
If SRAM is increased in the memory system controller, then translation operations can be performed, but resource utilization efficiency decreases
Solution Approach 1:
The translation operation capability is extracted from the embedded memory system controller and moved to the host system. This eliminates the need to allocate additional SRAM resources in the embedded controller, as the host system's memory and processing resources are used for translation instead, thereby maintaining translation capability while improving SRAM utilization efficiency in the embedded system
Data Source
AI summary
Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.