Managed NAND Host-Cached L2P With Feedback Validation
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Solution Overview
Problem
Current host-cached L2P techniques in memory devices are vulnerable to data corruption and unauthorized modifications due to the host's control over translation tables, lacking effective data validation and security measures.
Innovation Solution
Implement a verification mechanism using logical and physical address pairs, combined with encryption and sequence numbers, to ensure data integrity and protect proprietary operations by validating requests and obfuscating internal L2P mappings from the host.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If host-cached L2P techniques are implemented to enhance performance, then data access speed is improved, but data integrity and security are compromised due to vulnerability of translation tables
Solution Approach 1:
The system implements verification mechanisms where the memory device sends feedback signals to the host about the status of translation table entries. The host must provide valid responses to verification requests, creating a feedback loop that ensures data integrity while maintaining host-cached L2P performance benefits.
Solution Approach 2:
The patent introduces verification components and sequence numbers as intermediary elements between the host and memory device. These intermediaries validate the authenticity of translation table entries without requiring the host to have direct control over the L2P mappings, thus preventing data corruption while maintaining performance.
2Productivity
If the host controls translation tables to enable host-cached L2P operations, then operational efficiency is improved, but unauthorized modifications and data corruption become possible
Solution Approach 1:
The system performs preliminary verification actions before allowing host-cached L2P operations to proceed. The memory device verifies the host's control rights and the validity of translation table entries before enabling efficient operations, preventing unauthorized modifications while maintaining productivity.
Solution Approach 2:
The patent changes the parameters of translation table management by introducing sequence numbers and verification components. These parameter changes enable the system to track modifications and verify authenticity, allowing host-cached L2P operations to proceed securely without risking unauthorized changes.
3Speed
If translation tables are shared between host and memory device for performance optimization, then access speed is improved, but data security and proprietary operations are exposed
Solution Approach 1:
The system segments the translation table functionality by separating verification responsibilities. The host receives encrypted translation table entries and verification components, while the memory device maintains control over the actual L2P mappings. This segmentation allows performance optimization without exposing proprietary operations to the host.
Solution Approach 2:
The patent uses encrypted copies of translation table entries that the host can process without accessing the actual proprietary mappings. The memory device provides encrypted versions of L2P information that enable host-cached operations while preserving security, as the host works with encrypted copies rather than raw translation data.
Data Source
AI summary
Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.