Managed NAND Read Window Budget Detection by Voltage Sweep
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Solution Overview
Problem
Managed NAND (mNAND) systems lack robust, convenient, or reliable methods for detecting or calculating read window budget (RWB) in memory cells, which affects performance indicators such as program-erase cycle count, data retention rate, and programming speed.
Innovation Solution
A memory system measures RWB by using expected data patterns to determine the quantity of flipped bits at logic level edges through a voltage sweep operation, setting read voltages to different levels and outputting the current voltage level when a threshold of flipped bits is reached, allowing for improved performance by increasing PEC cycles, data retention time, and programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If managed NAND systems use conventional read methods, then device complexity is reduced, but measurement precision of read window budget is insufficient
Solution Approach 1:
The system performs preliminary actions by storing expected data patterns in SLC memory before the voltage sweep operation. This pre-prepared reference data enables accurate RWB measurement without requiring complex real-time comparisons during the sweep, thus improving measurement precision while controlling system complexity
Solution Approach 2:
The patent introduces SLC memory as an intermediary component to store expected data patterns. This intermediary enables the complex RWB measurement process to be broken down into manageable steps: storing reference data in SLC, performing voltage sweep on TLC data, and comparing results. The intermediary simplifies the overall system architecture while achieving precise measurements
2Measurement precision
If voltage sweep operation is performed to measure RWB, then measurement precision improves, but loss of time increases
Solution Approach 1:
By pre-storing expected data patterns in SLC memory, the system eliminates the need for time-consuming real-time data generation and comparison during the voltage sweep. The reference data is ready in advance, allowing the voltage sweep to focus solely on measuring bit flips at different voltage levels, thus reducing overall measurement time while maintaining precision
Solution Approach 2:
The patent implements a binary search approach to the voltage sweep operation, which skips unnecessary voltage levels by dividing the search space in half each time. This allows the system to quickly identify the read window budget by rapidly eliminating portions of the voltage range where bit flips are unlikely to occur, significantly reducing measurement time while preserving accuracy
3Quantity of substance
If multi-level cell programming is used, then quantity of substance (storage capacity) increases, but reliability decreases
Solution Approach 1:
The system changes the parameter of read voltage dynamically during the voltage sweep operation. By adjusting read voltages to different levels and observing bit flip patterns, the system can characterize the read window budget for each logic level edge. This parameter change approach enables the system to optimize read operations for high-density TLC storage while maintaining reliability through precise voltage control
Solution Approach 2:
The patent implements feedback by comparing read data at different voltage levels during the sweep operation. The system observes which bits flip at which voltage thresholds and uses this feedback information to accurately determine the read window budget. This feedback mechanism enables reliable characterization of multi-level cell storage properties, allowing optimized read operations that maintain data integrity in high-density storage
Data Source
AI summary
Methods, systems, and devices for establishing memory system read window budget (RWB) are described. A memory system may receive a command from a host system requesting an RWB for an edge of a distribution of a logic level of a set of logic levels. The memory system may determine an expected pattern of data corresponding to a set of memory cells and may store the expected pattern in memory. The memory system may perform a voltage sweep operation, including setting a read voltage to different levels across the edge for reading the set of memory cells. The memory system may count a quantity of expected bits resulting from a logic function of the expected pattern and the read data for each level, and may output a voltage offset corresponding to level at which a difference of the quantity of expected bits and an initial quantity satisfies a threshold.