Managed NAND Host Accelerated Operations Scrambling
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Solution Overview
Problem
Current host resident translation table systems (HRTTS) for managing NAND flash memory devices lack control over physical address access, leading to potential data corruption and unauthorized modifications, while traditional encryption methods are cumbersome and resource-intensive.
Innovation Solution
Implementing a scrambling technique using random numbers for physical addresses, where additional address bytes are used to index a key, allowing the memory device to reconstruct the physical address without revealing internal organization, and leveraging host memory for key storage to manage a virtually infinite number of scrambling keys.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional encryption methods are used for physical address protection, then data security is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent transforms the physical address through parameter changes by XORing selected bytes with corresponding bytes from a pseudorandom sequence. This simple bitwise operation provides encryption functionality without requiring complex cryptographic algorithms, thereby maintaining data security while reducing device complexity and resource consumption.
Solution Approach 2:
The patent uses a disposable pseudorandom sequence that is generated once and then discarded after use. Each sequence is used to encrypt physical addresses for a specific translation table load and then discarded, preventing reuse attacks. This approach provides strong security without requiring complex key management systems.
2Productivity
If host resident translation table systems are implemented, then address management efficiency is improved, but control over physical address access is lost leading to potential data corruption
Solution Approach 1:
The patent introduces an intermediary scrambling mechanism that sits between the host's address management and the actual physical address access. The physical addresses are scrambled using pseudorandom sequences before being used to access the translation table, creating a protective layer that maintains both the efficiency of host-resident translation tables and the integrity of data access.
Solution Approach 2:
The patent applies preliminary anti-action by pre-scrambling the physical addresses before they can be used to access sensitive data structures. This preemptive measure ensures that even if the host gains unauthorized access or the translation table is compromised, the actual physical addresses remain protected, preventing data corruption and unauthorized modifications.
Data Source
AI summary
Devices and techniques for host accelerated operations in managed NAND devices are described herein. A controller can receive an operation. Here the operation includes address data with a logical address portion and a physical address portion. The controller can then extract an index value and a location value from the physical address portion. The controller can retrieve a key using the index value and invoke a reversible function—using the index value and the location value—to produce a physical address. The controller can then perform the operation using the physical address.