Managed Runtime System Hybrid ISA Code Scheduling

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Hybrid computing architectures with different Instruction Set Architectures (ISAs) for performance and efficiency cores limit the utilization of CPU potential and innovation, as features supported by one type of core remain unused on the other.

Innovation Solution

A Managed Runtime System (MRS) that generates native code for each ISA and schedules it to the appropriate cores using a thread pool, allowing for the full potential of each core type to be exploited.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a compiler generates executable code for a dedicated architecture, then execution speed is improved, but portability to other architectures deteriorates

Engineering Contradiction:

Improveexecution speedVSAvoidportability

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent introduces a virtual machine as an intermediary layer between the compiled code and the hardware platforms. The compiler generates code for the virtual machine architecture rather than directly for specific hardware, and interpreters on each platform translate this intermediate code to native instructions. This mediator enables both fast execution (through optimized interpreters) and portability (through architecture-independent intermediate representation).

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system segments the compilation process into two distinct stages: compilation to virtual machine code (architecture-independent) and interpretation to native code (architecture-specific). This segmentation allows the compilation step to be performed once for multiple targets, improving portability, while the interpretation step optimizes for each specific platform, maintaining execution speed.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If an interpreter uses a virtual machine on each hardware platform, then portability is improved, but execution speed deteriorates

Engineering Contradiction:

ImproveportabilityVSAvoidexecution speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements dynamic code generation and optimization within the virtual machine environment. The system can adaptively compile frequently executed code paths to native code, optimize instruction sequences based on runtime performance data, and dynamically adjust the interpretation strategy. This dynamic approach bridges the gap between the portability of interpretation and the speed of native compilation.

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If hybrid architectures use different ISAs for performance and efficiency cores, then power efficiency is improved, but feature utilization deteriorates

Engineering Contradiction:

Improvepower efficiencyVSAvoidfeature utilization

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The virtual machine serves as a universal execution environment that can run the same intermediate code on both performance cores and efficiency cores with different ISAs. The system translates the architecture-independent intermediate representation to the appropriate native instructions for each core type, enabling efficiency cores to utilize advanced features (when available) while maintaining the ability to run on simpler architectures, thus achieving both power efficiency and feature utilization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Reliability

If features supported by performance cores are not supported on efficiency cores, then compatibility is improved, but productivity deteriorates

Engineering Contradiction:

ImprovecompatibilityVSAvoidCPU potential utilization

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system changes the representation parameters of the code from architecture-specific instructions to architecture-independent intermediate representation. This parameter change allows the same code to be executed on cores with different feature sets by translating to appropriate instruction sets at runtime, maintaining compatibility across different core types while enabling full utilization of available features on each core type through optimized code generation.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20230195426A1Method for Managing a Runtime System for a Hybrid Computing Architecture, Managed Runtime System, Apparatus and Computer Program

Publication Date: 2023.06.22 INTEL CORP

AI summary

Examples relate to a method for managing a runtime system for a hybrid computing architecture, a device, an apparatus and to a corresponding computer program. The apparatus is configured to create a thread pool for each work thread of a computer program, generate native code for at least one of the at least two ISAs for code segments of the computer program, assign native code sequences to a corresponding thread in the thread pool for execution, with the native code sequences comprising the native code of the code segments, and execute the native code sequences.