Managed Timing Engine Clock Switchover

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Solution Overview

Problem

Existing time and frequency alignment systems in packet-switched networks face challenges in maintaining precise timing when the Grand Master clock loses its reference, leading to potential outages due to time delays and clock drift in slave clocks, especially in mobile telephony systems.

Innovation Solution

Implementing a Managed Timing Engine that uses a high-performance oscillator disciplined by a physical layer reference to generate multiple time-base outputs with programmable frequency offsets, allowing for stable time alignment and minimizing transient impacts during switchover between timing references.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If distinct slave clocks are used for each grandmaster to enable rapid switchover, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvetiming continuity during GM failureVSAvoidnumber of clock hardware components

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple slave clock functions into a single physical slave clock by implementing multiple virtual clock instances through software. The single slave clock maintains multiple time-bases in memory, each associated with a different grandmaster, allowing rapid switchover between grandmasters without requiring multiple physical clock hardware components.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the slave clock functionality into separate software instances, where each instance maintains a specific time-base. This allows the system to treat multiple logical clocks as independent entities while physically implementing them in a single clock hardware, enabling rapid switchover by switching between software instances rather than physical hardware.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If multiple distinct phase-locked-loops are used to maintain multiple time-bases, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improvesupport for multiple timing referencesVSAvoidnumber of phase-locked-loop circuits

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a single phase-locked-loop that can be dynamically configured to track different grandmaster references. The PLL is designed to accept multiple input sources and can switch between them, providing universal functionality for maintaining multiple time-bases without requiring separate dedicated PLL circuits for each reference.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent makes the phase-locked-loop dynamic by allowing its target frequency and reference source to be changed in real-time through software control. This enables the single PLL to adaptively track different grandmaster frequencies and switch between time-bases as needed, providing the versatility of multiple dedicated PLLs with the simplicity of a single dynamic circuit.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10142044B2Managed timing engine

Publication Date: 2018.11.27 SKYWORKS SOLUTIONS INC

AI summary

A Managed Timing Engine (MTE) provides a primary timing output synchronized to a selected input reference from a multiplicity of input references. Additional timing outputs can be generated such that there is a programmable frequency offset (in ppb) between them and the main output. The rate (in Hz) of the outputs can be programmable. The MTE can introduce a programmable delay for periodic phase references.