Management Core Error Handling Without OS Interrupt Overhead

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Solution Overview

Problem

Existing computing systems inefficiently handle hardware errors by reporting them to the operating system, which can divert processing cycles from normal workload and require processor cores to pause, leading to inefficiencies.

Innovation Solution

Implement a management core within the processor that independently handles errors without visibility to the operating system, allowing processor cores to continue operations while errors are managed and logged in non-volatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If errors are reported to the operating system using existing interrupt systems, then error detection and reporting capability is improved, but processor cores must pause normal workload execution to handle errors, reducing productivity

Engineering Contradiction:
Improveerror detection and reporting capabilityVSAvoidprocessor core workload execution efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system is divided into two independent error handling paths: a first error handling mechanism that interfaces with the operating system for severe errors, and a second error handling mechanism that operates independently for correctable errors. This segmentation allows processor cores to handle different error types without pausing normal workload execution, resolving the contradiction between reliable error reporting and maintained productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A management core acts as an intermediary between processor cores and the operating system for error handling. The management core receives errors from processor cores, determines appropriate handling actions, and only involves the operating system when necessary. This intermediary mechanism enables independent error processing that maintains processor productivity while ensuring reliable error reporting through the management core's coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If every hardware error is reported to the operating system, then comprehensive error monitoring is improved, but processing cycles are diverted from normal workload, increasing loss of time

Engineering Contradiction:
Improvecomprehensive error monitoringVSAvoidprocessing cycle diversion from workload
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies partial action by implementing selective error reporting: not all errors are reported to the operating system, but only those requiring OS intervention. Correctable errors are handled independently by the management core or processor cores themselves, while severe errors are reported to the OS. This partial reporting approach maintains comprehensive error monitoring capability while minimizing time loss by avoiding unnecessary OS involvement for routine correctable errors.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of operation

If processor cores handle error reporting directly, then error handling simplicity is improved, but processing overhead increases and system complexity worsens

Engineering Contradiction:
Improveerror handling simplicityVSAvoiderror handling system complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The management core serves multiple functions: it handles error reporting for processor cores, manages communication with the operating system, determines appropriate error handling actions, and coordinates between different error handling mechanisms. This multi-functional design simplifies the overall system by consolidating error management responsibilities in a single component rather than requiring complex point-to-point error handling paths between each processor core and the OS.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260003718A1Error handling management core
Publication Date: 2026.01.01 ADVANCED MICRO DEVICES INC
  • US20260003718A1 patent drawing
  • US20260003718A1 patent drawing
  • US20260003718A1 patent drawing

AI summary

The disclosed device includes a processor core and a management core. The management core can intercept error interrupts indicating errors for the processor core. The management core can process the error while the processor core continues operations, and can also cloak the error from an operating system. The management core can also provide the errors to a baseboard controller for storing in a non-volatile memory. Various other methods, systems, and computer-readable media are also disclosed.