Manchester Receiver Clock Extraction for Jitter Tolerance
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Solution Overview
Problem
Manchester code receiving circuits face impaired jitter tolerance due to bit time distortion caused by differences in rising and falling times, leading to incorrect sampling and reduced performance.
Innovation Solution
The proposed solution involves a Manchester code receiving circuit with an edge interval counter and a clock extraction controlling module that adjusts count values based on analog circuit characteristics, ensuring constant sampling intervals and suppressing reception clock signal output under specific conditions to maintain jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a Manchester code receiving circuit uses a fixed clock extraction counter, then the circuit structure is simple, but the reception jitter tolerance is impaired due to bit time distortion from analog circuit characteristics
Solution Approach 1:
The clock extraction counter is transformed from a fixed structure to a dynamic one where the count value can be adjusted based on edge detection results. The controlling module modifies the count value dynamically to compensate for bit time distortion caused by analog circuit characteristics, thereby maintaining reliable reception despite jitter.
Solution Approach 2:
The system implements feedback by detecting edges of the reception signal and using this information to adjust the clock extraction counter's count value. The edge detection module provides feedback about actual signal transitions, which the controlling module uses to correct the sampling timing and compensate for distortions.
2Reliability
If the clock extraction counter count value is adjusted to compensate for bit time distortion, then the reception jitter tolerance is improved, but the device complexity increases
Solution Approach 1:
The receiving circuit is segmented into distinct functional modules: an edge detection module that identifies signal transitions, a controlling module that processes the detection results, and a clock extraction counter that performs sampling. This segmentation allows each module to have a specific, simplified function while the overall system achieves complex distortion compensation.
Solution Approach 2:
The edge detection module serves as an intermediary between the analog reception signal and the digital clock extraction counter. It detects transitions and provides timing information that mediates the adjustment of the counter's count value, enabling compensation without directly modifying the counter's internal structure.
3Speed
If the reception clock signal is output continuously, then the sampling rate is high, but incorrect sampling occurs due to bit time distortion from analog circuit characteristics
Solution Approach 1:
The system changes the parameter of the clock extraction counter's count value dynamically based on detected edge positions. By adjusting this parameter, the sampling timing is optimized for each bit period to compensate for bit time distortion, ensuring accurate sampling even when analog circuit characteristics cause timing variations.
Data Source
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AI summary
A Manchester code receiving circuit includes an analog circuit configured to convert an analog signal received through a communication transmission path, to a digital signal based on a Manchester code, and a characteristic compensating unit configured to compensate at least one of rise delay characteristics in which a rising time of the digital signal is longer than a falling time, and fall delay characteristics in which the falling time of the digital signal is longer than the rising time.