Differential Manchester Decoder Circuit for Short Pulse Detection
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Solution Overview
Problem
Existing decoders face challenges in accurately decoding differential Manchester encoding in the presence of noise and jitter, particularly when oversampling, as they struggle to distinguish between short and long pulses which are crucial for data demodulation.
Innovation Solution
A decoder circuit that down-samples oversampled signals from differential Manchester encoding by a factor of four, using a detector circuit to identify short and long pulses based on clock transitions and corresponding bit transitions, and generates additional down-sampled bits to assist in data demodulation, thereby improving decoding accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If oversampling is used to improve decoding accuracy in noisy conditions, then measurement precision is improved, but the ability to distinguish between short and long pulses deteriorates due to increased sample complexity
Solution Approach 1:
The patent segments the oversampled signal into groups of four consecutive samples and processes each group independently through a down-sampling circuit. This segmentation transforms the complex oversampled signal into manageable units, where each group produces a single down-sampled bit. The segmentation enables clear distinction between short pulses (producing specific down-sampled bit patterns) and long pulses (producing different patterns), thereby resolving the pulse distinction difficulty while maintaining decoding accuracy.
Solution Approach 2:
The patent changes the sampling rate parameter by downsampling the oversampled signal by a factor of four. The down-sampling circuit reduces the sample rate from the oversampled frequency to a lower frequency that maintains the essential pulse duration information. This parameter change simplifies the signal while preserving the ability to distinguish pulse lengths, as short pulses and long pulses produce fundamentally different patterns in the down-sampled domain.
2Device complexity
If down-sampling is applied to reduce sample rate, then device complexity is reduced, but decoding accuracy may deteriorate due to loss of fine temporal resolution
Solution Approach 1:
The patent applies preliminary down-sampling action to the oversampled signal before the main decoding process. The down-sampling circuit processes groups of four samples in advance, generating down-sampled bits that capture the essential pulse duration information. This preliminary action simplifies the subsequent decoding logic while maintaining accuracy, because the down-sampled bits already encode the distinction between short and long pulses in a form that is easy to decode.
Solution Approach 2:
The patent creates a simplified copy of the oversampled signal through down-sampling. The down-sampled bits serve as a compressed representation that preserves the critical pulse duration information needed for accurate decoding. This copying approach maintains decoding accuracy because the down-sampled signal faithfully represents the original pulse structure in a simplified form that is easier to process.
3Measurement precision
If additional down-sampled bits are generated to improve pulse distinction, then measurement precision is improved, but loss of time increases due to additional processing
Solution Approach 1:
The patent segments the processing into parallel down-sampling circuits that operate simultaneously on different groups of four samples. Each circuit generates down-sampled bits independently and in parallel, which improves pulse distinction accuracy without increasing sequential processing time. The segmented parallel architecture maintains high processing speed while producing the additional down-sampled bits needed for accurate pulse distinction.
Data Source
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AI summary
Decoder circuits and methods (200) down-sample the samples that oversample an input signal (100) having a differential Manchester encoding. A first input port (304) receives first, second, and third samples. A second input port (308) receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port (306) receives first, second, and third down-sampled bits. A detector circuit (322, 416) is configured to generate a detection signal (324, 420) indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down- sampled bit and the third sample. A generator circuit (330, 418) is configured to generate a fourth down-sampled bit (302, 414) that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.