Mandrel-Based Self-Aligned Patterning for IC Interconnection Lines
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Solution Overview
Problem
Current lithographic processes face challenges in achieving precise alignment and preventing misalignment issues at lower technology node sizes, leading to unwanted over-extension of dielectric blocks into neighboring interconnection lines, which can disrupt electrical continuity and cause premature failure.
Innovation Solution
The method involves forming patterns with alternating beta and gamma regions using a mandrel layer, etch mask layer, and spacer layer to create beta and gamma block mask portions that do not extend into adjacent lines, ensuring precise alignment and preventing over-extension through selective etching and anisotropic etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional lithographic processes are used to pattern dielectric blocks at lower technology node sizes, then manufacturing simplicity is maintained, but alignment precision deteriorates causing blocks to over-extend into neighboring lines
Solution Approach 1:
A mandrel layer is introduced as an intermediary structure between the dielectric layer and the pattern layer. The mandrels serve as alignment references that mediate the positioning of dielectric blocks, ensuring precise alignment without requiring direct lithographic alignment between blocks and neighboring lines. This intermediary layer absorbs the alignment tolerance issues.
Solution Approach 2:
The dielectric blocks are designed to self-align with the mandrels through the patterning process. The blocks automatically position themselves relative to the mandrel structures, eliminating the need for complex external alignment control. The mandrels essentially pattern the blocks through a self-aligned process.
2Reliability
If dielectric blocks are made larger to ensure they cut active lines without clipping, then reliability is improved, but they over-extend into neighboring lines causing electrical continuity disruption
Solution Approach 1:
The mandrel structures provide locally differentiated alignment references that define precise boundaries for each dielectric block. Each block is locally constrained by its associated mandrel, ensuring it cuts the intended active line while being prevented from over-extending into neighboring lines. The local mandrel-block relationship ensures proper sizing without global alignment issues.
Solution Approach 2:
The mandrels are formed in advance as alignment templates before the dielectric blocks are patterned. This preliminary action establishes the precise boundaries and positions for all subsequent block formations, ensuring that blocks are correctly sized and positioned to cut only their intended lines without affecting neighbors.
3Manufacturing precision
If lithographic overlay control is tightened to prevent block over-extension, then manufacturing precision is improved, but process complexity and cost increase
Solution Approach 1:
The process uses self-aligned patterning where the mandrels automatically define the block positions and sizes. The lithographic process simply needs to pattern blocks relative to the existing mandrels, which are already precisely positioned. This self-service approach eliminates the need for complex multi-step overlay control between different lithographic layers.
Solution Approach 2:
The mandrel layer acts as an intermediary that simplifies the lithographic overlay requirements. Instead of requiring precise direct alignment between dielectric blocks and underlying features, the mandrels serve as a intermediate reference layer that decouples these alignment requirements, allowing standard lithographic overlay control to suffice.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the tolerance to lithographic misalignment, preventing dielectric blocks from clipping neighboring lines and maintaining electrical continuity, thereby improving the reliability of interconnection systems in integrated circuits at smaller technology node sizes.
Implementation Method 1
Disposing a spacer layer over the structure, the spacer layer forming a beta trench plug in the beta trench and a gamma trench plug in the gamma trench
Implementation Method 2
Anisotropically etching the spacer layer to expose the beta and gamma trench plugs, and form an array of spacers disposed on sidewalls of the mandrels
Data Source
AI summary
A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.