Mandrel Spacer Patterning for Gate Separation
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the loss of interlayer insulating layers during the gate separation process, which affects the reliability and integration density of semiconductor devices, particularly due to the short channel effect and reduced design rules.
Innovation Solution
A method involving the formation of mandrel lines and spacer material layers on a hardmask layer, followed by a self-aligned patterning process to create a mask structure that minimizes the loss of interlayer insulating layers by exposing specific regions for gate-cutting, using stacked mandrel patterns and mandrel lines to form openings in the hardmask layer for precise gate separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate separation process is used, then the gate lines can be separated, but the interlayer insulating layer is lost during the process
Solution Approach 1:
The method forms a protective spacer layer on the interlayer insulating layer before the gate separation etching process. This preliminary protective structure prevents the interlayer insulating layer from being lost during subsequent etching operations, thereby maintaining reliability while avoiding material loss.
Solution Approach 2:
The spacer layer acts as an intermediary protective structure between the etching process and the interlayer insulating layer. It absorbs the harmful etching action, preventing direct contact with the interlayer insulating layer and eliminating material loss while still allowing the gate separation function to be achieved.
2Productivity
If design rules are reduced to increase integration density, then more devices can be integrated, but short channel effects increase and reliability deteriorates
Solution Approach 1:
The method changes the dimensional parameters of the gate structure by forming precise spacers with controlled widths. This allows the gate length to be accurately controlled at scaled dimensions, maintaining reliable transistor operation even as design rules are reduced to increase integration density.
Solution Approach 2:
The method replaces conventional direct patterning with a spacer-based self-aligned patterning approach. This substitution provides better dimensional control and reduces variability, enabling reliable device operation at smaller dimensions where short channel effects become significant.
3Ease of manufacture
If the gate separation process is performed without protective structures, then the process is simpler, but the interlayer insulating layer is damaged
Solution Approach 1:
The spacer layer is formed through self-aligned processes where the spacer automatically positions itself relative to the gate structure. This self-service approach maintains manufacturing simplicity while simultaneously achieving high precision in protecting the interlayer insulating layer, as the spacer forms precisely where needed without requiring additional alignment steps.
Data Source
AI summary
A method of manufacturing a semiconductor device may include forming a hardmask layer on gate lines and intergate insulating portions alternately arranged; respectively forming mandrel lines on regions of the hardmask layer, corresponding to every other one of the intergate insulating portions; conformally forming a spacer material layer, having a thickness corresponding to a width of the gate lines, on the hardmask layer; forming a mandrel material layer on the spacer material layer; removing a portion of the mandrel material layer to expose portions of the spacer material layer on an upper surface and a side surface of the mandrel line; removing the exposed portions of the spacer material layer to provide the mandrel lines and stacked mandrel patterns; and forming an opening in the hardmask layer, which exposes a gate-cut region of the gate lines, using the mandrel lines and the stacked mandrel patterns as a mask.