Semiconductor Structure Using Mandrel and Spacer Layers for Accurate Pattern Transfer

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Solution Overview

Problem

As semiconductor technology advances towards smaller process nodes, achieving accurate pattern transfer on wafers becomes challenging due to deformation or distortion of photoresist patterns, leading to reduced pattern accuracy and complexity in manufacturing.

Innovation Solution

A method involving the formation of discrete mandrel layers on a base, followed by spacer layers and a pattern transfer layer, where trenches are formed between spacer layers to improve pattern accuracy, allowing for precise control of trench sizes and positions, thereby enhancing the accuracy of the target pattern.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If photoresist patterns are used for direct patterning, then the manufacturing process is simple, but the pattern accuracy deteriorates due to deformation or distortion at small process nodes

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidpattern accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the patterning process into multiple steps: first forming mandrel layers with initial patterns, then using spacer layers to define final trench patterns. This segmentation allows the complex patterning to be broken down into simpler, more controllable steps that maintain accuracy at small process nodes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mandrel layers are formed in advance as preliminary structures that define the positions of future trenches. These mandrels serve as templates that guide subsequent spacer formation and pattern transfer, ensuring accurate pattern placement before the final etching step.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the process node size is reduced to increase functional density, then the circuit integration increases, but the pattern transfer accuracy deteriorates

Engineering Contradiction:
Improvefunctional densityVSAvoidpattern transfer accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces vertical dimensionality by forming three-dimensional mandrel structures and spacers that extend above the substrate surface. This vertical development allows precise lateral pattern definition through the spacer thickness, decoupling the lateral pattern accuracy from the limitations of photolithography at small process nodes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The spacer layers act as intermediary structures that transfer the pattern from the mandrels to the final trench structures. The spacers provide a controlled lateral offset from the mandrel positions, enabling precise trench placement that is independent of direct photolithography resolution limits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If mandrel layers are formed to occupy second trench positions, then the pattern accuracy of trenches improves, but the device complexity increases

Engineering Contradiction:
Improvetrench pattern accuracyVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The mandrel structures serve multiple functions: they define trench positions, guide spacer formation, and act as etch masks. The spacer layers automatically form at controlled distances from the mandrels through conformal deposition, self-defining the trench dimensions without requiring additional lithography steps for each trench.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11404273B2Semiconductor structure and forming method thereof
Publication Date: 2022.08.02 SEMICON MFG INT (SHANGHAI) CORP
  • US11404273B2 patent drawing
  • US11404273B2 patent drawing
  • US11404273B2 patent drawing

AI summary

The present disclosure provides a semiconductor structure and a forming method thereof. One form of a forming method includes: providing a base; forming a plurality of discrete mandrel layers on the base, where an extending direction of the mandrel layers is a first direction, and a direction perpendicular to the first direction is a second direction; forming a plurality of spacer layers covering side walls of the mandrel layers; forming a pattern transfer layer on the base, where the pattern transfer layer covers side walls of the spacer layers; forming a first trench in the pattern transfer layer between adjacent spacer layers in the second direction; removing a mandrel layer to form a second trench after the first trench is formed; and etching the base along the first trench and the second trench to form a target pattern by using the pattern transfer layer and the spacer layer as a mask. In the present disclosure, the accuracy of the pattern transfer is improved.