Manganese Interconnects for Void-Free Semiconductor Devices
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Solution Overview
Problem
The complexity of semiconductor device manufacturing leads to challenges such as void formation in conductive lines due to difficulties in filling high aspect ratio openings, resulting in increased contact resistance and reduced device performance.
Innovation Solution
Incorporating manganese-containing layers in the interconnect structures of semiconductor devices, specifically between conductive lines and dielectric layers, to prevent void formation and reduce contact resistance, with the manganese layers being made of manganese and the conductive lines made of copper, and using barrier layers to enhance the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional filling methods are used for high aspect ratio openings, then manufacturing process simplicity is maintained, but void formation occurs in conductive lines resulting in increased contact resistance
Solution Approach 1:
The patent applies composite materials by creating an interconnect structure with multiple layers including a barrier layer, copper fill, and manganese-containing layer. This composite structure addresses the void formation problem by combining materials with different properties: the barrier layer prevents diffusion, the copper provides conductivity, and the manganese-containing layer fills voids and reduces contact resistance, thereby improving reliability without excessive complexity increase
Solution Approach 2:
The patent implements local quality by placing the manganese-containing layer specifically at the interface between the conductive line and the dielectric layer, and within high aspect ratio openings where voids are most problematic. This localized application targets the specific regions needing improvement (contact areas) rather than uniformly modifying the entire interconnect structure, thus improving contact resistance while controlling complexity
2Reliability
If barrier layers are added to prevent void formation, then contact resistance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the barrier layer and manganese-containing layer before filling the conductive material. The barrier layer is deposited first to prevent void formation and control interface quality, followed by the manganese-containing layer that further prevents voids and reduces contact resistance. This preliminary preparation of the interface structure ensures low contact resistance while the sequential deposition process integrates smoothly into existing manufacturing workflows
Data Source
AI summary
The present disclosure provides a semiconductor device structure with a manganese-containing interconnect structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first interconnect structure disposed in a semiconductor substrate, a dielectric layer disposed over the semiconductor substrate, and a second interconnect structure disposed in the dielectric layer and electrically connected to the first interconnect structure. The first interconnect structure includes a first conductive line, and a first manganese-containing layer disposed over the first conductive line. The second interconnect structure includes a second conductive line, and a second manganese-containing layer disposed between the second conductive line and the dielectric layer.