Multi-Precision Mantissa Aligner for Floating Point Multiply Accumulator
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
State-of-the-art floating point multiply accumulators (FMACs) are incapable of improving power usage, overhead efficiency, and flexibility due to the lack of support for parallel single-precision operations, which limits their ability to reduce complexity and enhance performance.
Innovation Solution
The implementation of a processing device with shared bit-shifting circuitry that enables parallel operation of first, second, and third precision circuits, allowing for simultaneous exponent addition and mantissa multiplication, thereby facilitating multi-precision mantissa alignment and optimizing power and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If state-of-the-art FMACs are used without parallel single-precision operations, then device complexity is reduced, but power usage efficiency and flexibility deteriorate
Solution Approach 1:
The FMAC is segmented into multiple precision operation circuits (first precision, second precision, third precision) that can operate in parallel. Each precision circuit handles different precision requirements, allowing the system to process multiple operations simultaneously without requiring a complete redesign of the entire FMAC architecture.
Solution Approach 2:
The shared bit-shifting circuit serves multiple precision operation circuits, providing a universal resource that supports different precision operations. This multi-functional approach allows the same hardware resource to be utilized by multiple precision circuits, improving power efficiency without proportionally increasing device complexity.
2Productivity
If parallel single-precision operations are added to FMAC, then flexibility and throughput are improved, but device complexity increases
Solution Approach 1:
Multiple precision operation circuits are merged into a single FMAC architecture with shared resources. The first, second, and third precision operation circuits share the bit-shifting circuit and other common infrastructure, allowing parallel operations to occur without proportionally increasing the overall device complexity.
Solution Approach 2:
The FMAC architecture dynamically supports multiple precision operations through configurable precision circuits. The system can adaptively select and execute operations at different precision levels based on computational requirements, enabling flexible throughput improvement without static complexity increase.
3Area of stationary object
If shared bit-shifting circuit is used for multiple precision circuits, then area usage is optimized, but circuit overhead increases
Solution Approach 1:
The bit-shifting circuit is designed as a universal shared resource that serves multiple precision operation circuits. This single circuit performs bit-shifting operations for first precision, second precision, and third precision circuits, optimizing area usage by eliminating redundant bit-shifting hardware while managing overhead through centralized control.
4Use of energy by moving object
If multi-precision mantissa alignment is implemented, then power usage is reduced, but device complexity increases
Solution Approach 1:
Mantissa alignment is performed as a preliminary action before final computation operations. By pre-aligning mantissas across different precision circuits, the system reduces the computational complexity and power requirements of subsequent operations, as alignment is handled by the shared bit-shifting circuit rather than requiring complex real-time adjustment mechanisms.
Data Source
AI summary
A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.