Floating-Point Mantissa Bit Extension for Concurrent Summation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for processing floating-point numbers, such as accumulation and binary tree adders, suffer from rounding errors and significant delays, especially when dealing with large arrays of numbers.
Innovation Solution
A hardware implementation and method that processes a set of k floating-point numbers by converting them into a second format with extended bit length, aligning based on a maximum exponent, and performing concurrent processing to achieve accurate and efficient summation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential accumulation is used to add floating-point numbers, then hardware complexity is reduced, but processing time increases and rounding errors occur
Solution Approach 1:
The patent segments the floating-point addition process into distinct stages: exponent alignment, mantissa extension, parallel addition, and result normalization. This segmentation allows each stage to be optimized independently and enables concurrent processing of multiple operations, reducing overall processing delay while managing hardware complexity through modular design
Solution Approach 2:
The patent performs preliminary actions by pre-extending the mantissa bit length before addition and pre-aligning exponents to the maximum value. This preliminary preparation eliminates the need for iterative adjustment during the addition process, significantly reducing processing time while maintaining accuracy
2Device complexity
If sequential accumulation is used to add floating-point numbers, then hardware resources are minimized, but rounding errors accumulate
Solution Approach 1:
The patent extends the mantissa bit length in advance before the addition operation. This preliminary extension provides additional precision bits that are maintained throughout the calculation process, preventing rounding errors from accumulating. The extended precision is then normalized back to the original bit length after addition, ensuring both accuracy and efficient hardware utilization
Solution Approach 2:
The patent changes the parameter of mantissa bit length from the standard fixed length to an extended length during the addition process. This parameter change allows for higher precision intermediate calculations while using the same hardware resources for both the extended precision mode and the final normalized output, effectively resolving the precision-hardware complexity trade-off
3Productivity
If multiple floating-point adders are used to increase throughput, then processing speed improves, but device complexity increases
Solution Approach 1:
The patent merges multiple addition operations into a single concurrent processing unit that can handle multiple floating-point numbers simultaneously. By combining the alignment, extension, and addition functions into one integrated unit, the patent achieves high throughput without proportionally increasing hardware complexity. The merged design shares common resources such as control logic and data paths among multiple operations
Solution Approach 2:
The patent transitions from sequential time-based processing to parallel space-based processing by introducing a new dimension of concurrent operation. Multiple floating-point numbers are processed simultaneously in different time steps within a single clock cycle, effectively increasing throughput. This dimensional change from sequential to parallel processing achieves high productivity without requiring a linear increase in hardware complexity
Data Source
AI summary
A method and system for processing a set of ‘k’ floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (mi) and an exponent (ei). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (mi). The method includes identifying a maximum exponent (emax) among the exponents ei, aligning the magnitude bits of the numbers (yi) based on the maximum exponent (emax) and processing the set of ‘k’ numbers concurrently.