Block Floating-Point Mantissa Bit-Width Adjustment for Neural Network Efficiency

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Solution Overview

Problem

Conventional methods for processing artificial neural networks with large input data are inefficient, as they struggle to effectively extract information due to high computational requirements and inaccuracies at low precision levels, especially in sequence transduction models.

Innovation Solution

A processor-implemented method that adjusts the bit-width of the mantissa in floating-point data based on the exponent size, comparing it to a threshold determined by the data distribution and allowable error range, to optimize operations and reduce computational complexity while maintaining accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional fixed-point or integer quantization methods are used, then hardware implementation is simplified, but inference accuracy deteriorates at very low word sizes due to inadequate dynamic range

Engineering Contradiction:
Improvehardware implementation complexityVSAvoidinference accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements block floating-point representation where the exponent is shared across a block of mantissas, allowing dynamic adjustment of the dynamic range. This enables the system to adapt to varying data distributions while maintaining hardware efficiency, resolving the contradiction between simplified hardware and adequate dynamic range for low precision.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the numerical representation parameters by introducing block floating-point format with shared exponents and optimized mantissa bit-widths. This parameter change allows the system to achieve both hardware simplicity and sufficient dynamic range by fundamentally altering how numbers are represented and processed.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If uniform floating-point representation is used, then dynamic range is maximized, but computational efficiency deteriorates due to variable precision requirements

Engineering Contradiction:
Improvedynamic range coverageVSAvoidcomputational efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the floating-point representation into blocks where multiple values share a common exponent. This segmentation allows uniform treatment of exponent management while reducing the overall computational burden by processing groups of values together rather than individually, thus improving computational efficiency while maintaining dynamic range.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shared exponent structure provides universal handling for multiple mantissas within a block, allowing a single exponent management mechanism to serve multiple values. This multi-functional approach improves computational efficiency by eliminating redundant exponent operations while maintaining the dynamic range benefits of floating-point representation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If higher precision floating-point is used, then inference accuracy is improved, but energy consumption and computational complexity increase

Engineering Contradiction:
Improveinference accuracyVSAvoidenergy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent optimizes the precision parameters by using block floating-point with shared exponents and carefully selected mantissa bit-widths. This parameter optimization maintains inference accuracy by preserving sufficient precision where needed while reducing the overall bit-width and computational complexity, thereby lowering energy consumption.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4141646B1Method and apparatus with calculation
Publication Date: 2024.03.13 SAMSUNG ELECTRONICS CO LTD
  • EP4141646B1 patent drawingFigure 1A
  • EP4141646B1 patent drawingFigure 1B
  • EP4141646B1 patent drawingFigure 1C

AI summary

A processor-implemented method includes: receiving a plurality of pieces of input data expressed as floating point; adjusting a bit-width of mantissa by performing masking on the mantissa of each piece of the input data based on a size of an exponent of each piece of the input data; and performing an operation between the input data with the adjusted bit-width.