Many-Core Synchronization Barrier Using N-Way Shuffle
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Solution Overview
Problem
Current synchronization barriers in multithreaded computing are limited by cache misses, leading to inefficiencies and increased latency, particularly in cache-based processor architectures, as threads communicate to cross synchronization points.
Innovation Solution
The implementation of a computing device that alternates between remote and local synchronization, using an n-way perfect shuffle configuration to reduce cache misses and improve performance, with support for transactional synchronization barriers compatible with OpenMP tasking semantics, by employing a processor with multiple cores and hardware threads that share a private cache, and utilizing a barrier network to synchronize threads across processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional tree barriers are used for synchronization, then threads can coordinate across processor cores, but cache misses increase and latency increases
Solution Approach 1:
The barrier synchronization is segmented into multiple levels: local barriers within each processor core and remote barriers between cores. Threads first synchronize locally with other threads on the same core, then synchronize remotely with threads on other cores. This segmentation reduces the scope of cache coherence traffic at any given time, thereby reducing cache misses and latency.
Solution Approach 2:
The patent introduces an n-way perfect shuffle dimension to the traditional tree barrier structure. Instead of a simple hierarchical tree, threads are remapped using a perfect shuffle function that distributes threads across different processor cores in a balanced manner. This dimensional transformation optimizes the communication pattern and reduces cache conflict misses.
2Reliability
If threads wait on each other in tree pattern for barrier synchronization, then all threads can be coordinated, but the number of cache misses increases
Solution Approach 1:
The barrier operation is divided into local and remote phases. In the local phase, threads on the same processor core synchronize using shared cache lines, minimizing external memory accesses. In the remote phase, threads synchronize with threads on other cores through a reduced number of cache-coherent operations. This segmentation reduces the total number of cache misses and associated energy consumption.
Solution Approach 2:
Multiple threads that would traditionally synchronize separately in a tree pattern are merged into groups that synchronize simultaneously through the perfect shuffle mapping. This merging reduces the total number of synchronization operations and cache misses required to complete the barrier.
3Reliability
If traditional barrier synchronization is implemented, then threads can synchronize, but performance is limited by cache coherence overhead
Solution Approach 1:
The patent implements dynamic barrier scheduling where threads can proceed through different phases of synchronization based on their local state. The barrier operation adapts to the actual distribution of threads across cores and their execution states, allowing flexible progression through local and remote synchronization phases without rigid sequential constraints.
Solution Approach 2:
The perfect shuffle mapping transforms the traditional one-dimensional tree barrier into a multi-dimensional synchronization structure. This dimensional change optimizes the communication topology and reduces cache coherence overhead by distributing synchronization traffic more evenly across the processor interconnect.
Data Source
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AI summary
Technologies for multithreaded synchronization including a computing device having a many-core processor. Each processor core includes multiple hardware threads. A hardware thread executed by a processor core enters a synchronization barrier and synchronizes with other hardware threads executed by the same processor core. After synchronization, the hardware thread synchronizes with a source hardware thread that may be executed by a different processor core. The source hardware thread may be assigned using an n-way shuffle of all hardware threads, where n is the number of hardware threads per processor core. The hardware thread resynchronizes with the other hardware threads executed by the same processor core. The hardware thread alternately synchronizes with the source hardware thread and the other hardware threads executed by the same processor core until all hardware threads have synchronized. The computing device may reduce a Boolean value over the synchronization barrier. Other embodiments are described and claimed.