Many-Core Inter-Process Communication via Cache Pre-Fetching

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Solution Overview

Problem

In many-core processors, the existing inter-core communication methods, such as shared memory and IPI, lead to slower message body reading speeds, degrading user experience due to the need for direct access to shared memory.

Innovation Solution

A method where a target kernel acquires a message header from a Quick Message Channel, executes a CPU pre-fetching command to load the message body into the cache of the target processor core, and switches to the target process, allowing the message body to be read directly from the cache without accessing shared memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the user-layer application reads the message body from shared memory, then the message body can be accessed, but the reading speed decreases and user experience degrades

Engineering Contradiction:
Improvemessage body reading speedVSAvoiduser experience
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The system pre-loads the message body from shared memory into the cache of the target processor core before the user-layer application needs to access it. The target kernel detects the message arrival, executes a CPU pre-fetching command to load the message body into cache, and then switches to the target process, so that when the application reads the message, it is already in the cache and can be accessed at high speed.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If direct access to shared memory is used for inter-core communication, then communication between cores is enabled, but the communication efficiency is reduced

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidmessage body reading speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The cache of the target processor core serves as an intermediary between the shared memory and the user-layer application. Instead of the application directly accessing shared memory, the message body is first transferred to the cache (which is much faster), and then the application accesses it from the cache. This intermediary cache memory resolves the contradiction by providing fast access while maintaining the shared memory architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2908246B1Method, device and system for inter-process communication of many-core processor
Publication Date: 2018.03.21 HUAWEI TECH CO LTD
  • EP2908246B1 patent drawingFigure 1
  • EP2908246B1 patent drawingFigure 2
  • EP2908246B1 patent drawingFigure 3

AI summary

Embodiments of the present invention provide a method, an apparatus, and a system for mutual communication between processes of a many-core processor, and relate to the field of many-core operating systems, so as to increase the speed of reading a message body and enhance user experience. The method is executed by a target kernel Kernal, where the target kernel corresponds to a target processor core. The method includes: acquiring a message header of a message from a quick message channel QMC; executing a CPU pre-fetching command according to the message header, so that a message body that is in the message stored in a shared memory and corresponds to the message header is loaded to a cache cache that corresponds to the target processor core; and switching to a target process, so that the target process acquires the message body from the cache. The embodiments of the present invention apply to a scenario of mutual communication between processes of a many-core processor.