Configurable Many-Core Processor Event Bus Synchronization
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Solution Overview
Problem
Conventional many-core processors lack efficient hardware synchronization mechanisms and flexible data movement capabilities, particularly in embedded systems with high real-time requirements, due to inefficient synchronization methods and limited on-chip memory space definition.
Innovation Solution
An embedded-oriented configurable many-core processor design featuring an on-chip data-bus system, event-bus system, and integrated routing units with configuration registers, allowing for direct core-to-core communication through events and flexible data transmission paths, including static and dynamic routing for high throughput and low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If soft synchronization using synchronization packages is used, then synchronization can be achieved, but synchronization speed is slow and real-time performance is poor
Solution Approach 1:
The patent replaces the software-based synchronization package mechanism with a hardware-level event bus system. Event control units directly generate and distribute event signals through dedicated hardware pathways, eliminating the need for software packet processing and significantly accelerating synchronization speed while maintaining manageable system complexity through standardized event handling protocols.
Solution Approach 2:
The event bus serves as a dedicated intermediary hardware structure that facilitates direct communication between event control units and core sets. This intermediary layer enables efficient event signal distribution without requiring complex software coordination, resolving the contradiction between fast synchronization and system complexity.
2Adaptability or versatility
If on-chip memory space is limited, then chip area is reduced, but data movement flexibility is insufficient
Solution Approach 1:
The patent segments memory resources into distributed memory units associated with each core set rather than using a large centralized memory. This segmentation allows each core set to have dedicated memory space while enabling flexible data movement between segments through the event bus, achieving both area efficiency and adaptability.
Solution Approach 2:
The event bus system provides dynamic data movement capabilities that allow flexible routing of data between core sets and memory units based on real-time requirements. This dynamic routing mechanism achieves high data movement flexibility without requiring excessive on-chip memory area, as data is routed efficiently rather than pre-allocated.
3Productivity
If multiple cores are integrated to provide ultra-high computing performance, then processing power increases, but synchronization between cores becomes more difficult
Solution Approach 1:
The event bus system serves as a universal synchronization mechanism that handles all inter-core-set communication needs. Each event control unit can generate various types of events (synchronization, data transfer, control signals) through the same hardware infrastructure, ensuring reliable coordination across multiple core sets while maintaining high computing performance.
Data Source
AI summary
An embedded-oriented configurable many-core processor is disclosed, which includes: an on-chip data-bus system, an on-chip event-bus system, a data connection line, a routing unit and a core. The on-chip data-bus system includes multiple transverse data-bus and vertical data-bus. The multiple transverse data-bus and vertical data-bus are staggered transversely and vertically to form N intersections, each intersection of the N intersections is correspondingly provided with a routing unit, and adjacent routing units are connected by transverse data-bus or vertical data-bus. The on-chip event-bus system includes: an event control unit, an event bus and an event signal line. Each event control unit is connected with the event bus, and is connected with the corresponding core and routing unit through the event signal line.