Many-Core Shared Storage Routing for Parallel Memory Access
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Solution Overview
Problem
The current many-core processor storage systems face limitations such as fixed address spaces, lack of support for ping pong operations, and inflexible memory module combinations, which hinder processor performance and efficiency.
Innovation Solution
A many-core definable distributed shared storage structure is introduced, featuring a routing table system with network interface units, routing units, and memory modules, allowing flexible address mapping and support for ping pong operations through definable routing tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a centralized shared storage system is used, then the structure is simple and data synchronization is easy, but the memory access time is long and system scalability is poor
Solution Approach 1:
The patent divides the centralized storage system into multiple distributed storage units, each accessible by multiple processor cores. This segmentation allows parallel access to different storage units, improving memory access speed while maintaining manageable system complexity through modular architecture.
Solution Approach 2:
The patent introduces a new dimension of access parallelism by allowing multiple processor cores to simultaneously access different storage units. This transforms the single-dimensional sequential access model into a multi-dimensional parallel access model, significantly improving memory access speed.
2Productivity
If the number of processor cores is increased, then the computing capacity is exponentially increased, but the storage wall bottleneck becomes increasingly severe
Solution Approach 1:
The patent segments the storage system into multiple independent storage units that can be simultaneously accessed by different processor cores. This segmentation increases the total storage bandwidth available to the many-core system, preventing the storage wall bottleneck that occurs when scaling up processor cores.
Solution Approach 2:
The patent creates a multi-functional storage architecture where each storage unit can serve multiple processor cores, and each processor core can access multiple storage units. This universality ensures that storage bandwidth scales proportionally with computing capacity.
3Adaptability or versatility
If a distributed storage system is used, then the system scalability is improved and data locality is enhanced, but the access-storage operation becomes asymmetric and data synchronization delay increases
Solution Approach 1:
The patent implements local quality by allowing each processor core to have preferred access to specific storage units containing frequently accessed data. This enhances data locality and access efficiency while maintaining the scalability benefits of distributed storage.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors access patterns and dynamically adjusts data placement and routing to minimize synchronization delays. This feedback loop ensures that data is positioned optimally to reduce synchronization time while maintaining system scalability.
4Device complexity
If a fixed address space is used, then the storage structure is simple, but the processor adaptability for different applications is reduced
Solution Approach 1:
The patent implements a dynamic address space configuration where the mapping between processor cores and storage units can be reconfigured based on application requirements. This dynamic adaptability allows the system to optimize performance for different workloads without increasing fundamental structural complexity.
Solution Approach 2:
The patent allows changeable address space parameters such as the number of address groups, banks, and their mappings. These parameter changes enable the system to adapt to different application needs while maintaining a relatively simple underlying storage structure.
Data Source
AI summary
Provided is a many-core definable distributed shared storage structure including: a plurality of routing units, a plurality of processor cores, a plurality of the network interface units, and a plurality of memory modules. Each network interface unit includes a configuration package parsing unit, a data packet assembling/parsing unit, and a routing table. The configuration package parsing unit parses a configuration package acquired from the routing unit by judging an operation type by a packet header: extracting address information and data information in the configuration package; and combining the operation type, the address information and the data information, to obtain and output a routing configuration instruction and a routing control instruction to the routing table. The routing table supports judgment and query, in response to the address signal, of a physical coordinate position of a destination memory module, and provides said physical coordinate position for the data packet assembling/parsing unit.