Hardware Memory Address Translation in Manycore Systems
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Solution Overview
Problem
Existing manycore systems face challenges in translating memory addresses without an operating system, particularly in bare-metal systems and resource-constrained environments, as existing methods require additional computing resources and are inefficient for specific-function systems.
Innovation Solution
A method and system for translating memory addresses in a manycore system that receives thread identification information and virtual addresses, calculates an address correction value to determine physical addresses, allowing for hardware-based translation without operating system intervention, using a memory access module to manage memory access across multiple cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing multi-threading address translation technique is used, then virtual address to physical address translation is achieved, but additional computing resources are required to execute the operating system
Solution Approach 1:
The patent extracts the address translation function from the operating system environment and implements it directly in hardware within the manycore system. The address translation unit is integrated into the processor architecture, allowing virtual-to-physical address translation to occur without requiring an operating system or additional software layers, thereby reducing computing resource requirements while maintaining translation capability
Solution Approach 2:
The patent introduces a thread identifier-based mapping mechanism as an intermediary between virtual addresses and physical addresses. Instead of using traditional page tables managed by an OS, the system uses thread identifiers to directly map virtual address segments to physical address segments, enabling efficient address translation in bare-metal environments without requiring operating system intervention
2Reliability
If operating system-based address translation is used, then address translation is performed, but the method is difficult to use in bare-metal systems and embedded environments
Solution Approach 1:
The manycore system performs address translation autonomously using integrated hardware components and thread identifier-based mapping. The system serves its own address translation needs without external operating system support, making it adaptable to bare-metal and embedded environments where minimal external software is available
Solution Approach 2:
The patent changes the fundamental parameters of address translation by replacing OS-managed page tables with hardware-based thread identifier mapping. This parameter change enables the system to operate in environments without traditional operating systems, expanding adaptability across different computing platforms
3Reliability
If traditional address translation method is used, then virtual address translation is achieved, but it is inefficient for systems designed for specific functions with resource constraints
Solution Approach 1:
The patent segments the address space into fixed-size segments and uses thread identifiers to map virtual segments to physical segments. This segmentation approach simplifies the address translation process compared to traditional page-based methods, reducing translation overhead and improving efficiency in resource-constrained systems
Solution Approach 2:
The system implements address translation only when needed for specific thread accesses, rather than maintaining full virtual memory management infrastructure. This partial action approach reduces resource consumption while maintaining necessary translation capability for multi-threaded operations
Data Source
AI summary
A method for translating memory addresses in a manycore system is provided, which is executed by one or more processors, and includes receiving identification information of a thread accessing a memory associated with one or more cores of a cluster that includes a plurality of cores, receiving a virtual address of data accessed by the thread, and determining a physical address of data in the memory based on the virtual address and the identification information of the thread.