Parallel MAP Decoder with Scan-Based Transition Matrix Products
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Solution Overview
Problem
Existing MAP decoders face inefficiencies in hardware implementation due to computational intensity, particularly in noisy channel environments, where parallel processing is limited by sequential calculation methods.
Innovation Solution
Implementing a parallel MAP decoder using a scan algorithm across multiple processing units in a Technical Computing Environment (TCE), allowing for efficient calculation of cumulative products of transition matrices and initialization vectors, thereby facilitating parallel computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential calculation methods are used in MAP decoder, then computational accuracy is maintained, but processing speed and efficiency deteriorate
Solution Approach 1:
The patent divides the MAP decoder computation into multiple independent processing units, each handling specific segments of the trellis diagram calculations. The forward recursion and backward recursion operations are segmented across different processing units, allowing parallel execution of matrix multiplications and cumulative product calculations that were previously performed sequentially.
Solution Approach 2:
The patent transitions from sequential single-threaded computation to parallel multi-dimensional processing by organizing calculations across multiple processing units working simultaneously. This dimensional expansion allows the system to compute multiple states and transitions in parallel, fundamentally changing the computational architecture from linear to parallel processing.
2Productivity
If parallel processing is implemented in MAP decoder, then processing efficiency is improved, but hardware complexity increases
Solution Approach 1:
The patent designs processing units that can perform multiple functions: calculating forward recursion values, computing backward recursion values, and performing matrix multiplications. Each processing unit is universally capable of handling different stages of the MAP algorithm, reducing the need for specialized dedicated hardware for each function and thereby managing hardware complexity.
Solution Approach 2:
The patent uses identical copies of processing units arranged in parallel to handle different segments of the computation. Rather than designing complex unique circuits for each function, the system replicates a standardized processing unit template, simplifying hardware design and implementation while achieving parallel processing capabilities.
3Use of energy by moving object
If computational intensity is reduced in MAP decoder, then hardware resource consumption decreases, but decoding accuracy may deteriorate
Solution Approach 1:
The patent replaces complex sequential computational mechanics with parallel computational mechanics. By distributing calculations across multiple processing units that operate simultaneously, the system reduces the temporal accumulation of computational intensity in a single unit, thereby lowering peak energy consumption while maintaining overall computational accuracy through parallel verification and consistent algorithmic execution.
Data Source
AI summary
A MAP decoder may be implemented in parallel. In one implementation, a device may receive an input array that represents received encoded data and calculate, in parallel, a series of transition matrices from the input array. The device may further calculate, in parallel, products of the cumulative products of the series of transition matrices and an initialization vector. The device may further calculate, in parallel and based on the products of the cumulative products of the series of transition matrices and the initialization vector, an output array that corresponds to a decoded version of the received encoded data in the input array.