Memory Controller Map Table Update Parallelism
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Solution Overview
Problem
The existing memory systems face inefficiencies in updating map table data during write requests, as the time required for updating map data adds to the overall processing time, and existing solutions do not effectively parallelize the map table update operation with data programming in flash memory devices.
Innovation Solution
A memory system and controller architecture that includes an external interface circuit and a processor to perform a map table update operation in parallel with data programming by using a shared memory region to store and manage write logical addresses and data, allowing the external interface circuit to initiate the map table update before receiving the write data, thereby overlapping the update and programming intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the map table update operation is performed sequentially after data programming, then the map data is updated accurately, but the overall processing time increases
Solution Approach 1:
The patent applies preliminary action by having the external interface circuit receive and store the write logical address in the map table before the actual data programming is completed. This allows the map table update to start in advance, overlapping with the programming operation, thus reducing the overall processing time while maintaining update accuracy through the use of a dedicated storage location for the write logical address
2Productivity
If the map table update operation is performed in parallel with data programming, then the processing time is reduced, but the system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the write operation into distinct functional parts: the external interface circuit handles map table updates using the write logical address, while the processor handles data programming. This segmentation allows parallel execution of both operations without requiring complex coordination mechanisms, thus achieving improved write speed with minimal increase in system complexity
Solution Approach 2:
The patent uses the write logical address as an intermediary element that enables parallel operation. The external interface circuit receives and stores this address in a specific storage location within the map table, which then serves as a reference for the processor to perform data programming. This intermediary mechanism simplifies the parallelization process by providing a clear handoff point between the two concurrent operations
Data Source
AI summary
A memory system may include a storage device, an external interface circuit configured to receive a write logical address associated with a write command and a storage location for mapping information and store the write logical address in the storage location; and a processor configured to determine the storage location at which the write logical address is to be stored within a map table and control the storage device to program write data associated with the write command, the map table storing map data between external logical addresses and physical addresses of the storage device.