Mapped FIFO Buffering for Network Interface Devices
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Solution Overview
Problem
Conventional network interface devices (NICs) face inefficiencies in buffer memory utilization due to dedicated fixed-size FIFO buffers, leading to underutilization of memory resources, especially with varying port throughputs and increased buffering demands from higher speed Ethernet standards and protocols that do not tolerate packet loss.
Innovation Solution
A network interface device with a unified memory architecture featuring virtual queues and dynamic buffer allocation, where data packets are written contiguously to linked logical sequences of buffers, allowing for efficient use of memory across multiple ports and prioritization of data flows, and dynamic buffer allocation from common and private pools based on queue needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated fixed-size FIFO buffers are provided for each physical port, then each port has sufficient buffer capacity to avoid packet loss, but buffer memory utilization is poor when port throughputs vary
Solution Approach 1:
The patent merges the previously separate dedicated FIFO buffers for multiple physical ports into a single shared buffer memory. The shared buffer is logically divided into port-specific regions that can be dynamically allocated and shared among ports based on actual throughput needs, eliminating the waste of unused buffer space in dedicated architectures while maintaining packet loss prevention.
Solution Approach 2:
The patent introduces dynamic buffer allocation mechanisms where buffer regions are not fixed but can be reallocated among ports based on varying throughput demands. The buffer memory manager dynamically adjusts the size and assignment of buffer regions to active ports, ensuring that buffer capacity follows actual traffic patterns rather than remaining static as in dedicated FIFO architectures.
2Productivity
If fixed-size buffers are designed to accommodate maximum packet size, then large packets can be handled without linking, but smaller packets leave unused memory space
Solution Approach 1:
The patent segments the shared buffer memory into multiple variable-sized regions that can be dynamically allocated based on actual packet sizes. Instead of using fixed-size buffers that must accommodate maximum packet dimensions, the buffer manager divides the shared memory into smaller segments that match the actual data being transmitted, eliminating wasted space while maintaining high-speed packet handling capabilities.
Solution Approach 2:
The patent changes the buffer size parameter from fixed to variable, allowing buffer regions to be dynamically resized based on packet size requirements. The buffer memory manager allocates buffer regions with sizes matched to actual packet dimensions rather than maximum possible sizes, optimizing memory utilization while preserving high-speed packet processing.
3Adaptability or versatility
If multiple physical ports are supported with dedicated buffers, then each port can operate independently, but total buffer memory requirements increase with each additional port
Solution Approach 1:
The patent makes the buffer memory universal by creating a shared resource that serves multiple physical ports simultaneously. The shared buffer can be dynamically allocated to serve any combination of active ports, allowing the same physical memory to fulfill the buffering needs of multiple ports rather than requiring separate dedicated buffers for each port.
Solution Approach 2:
The patent introduces asymmetric buffer allocation where ports receive unequal buffer sizes based on their actual throughput requirements rather than equal fixed allocations. The buffer memory manager continuously monitors port activity and allocates larger buffer regions to high-throughput ports while reducing allocations to low-activity ports, optimizing total memory usage while maintaining multi-port operational capability.
Data Source
AI summary
A network interface device for connection between a network and a data processing system, the network interface device comprising: a plurality of ports for receiving data packets directed to the data processing system. An interface services the ports in a predetermined order and writes the data packets to buffers of a common memory. Each buffer is part of one of a set of linked logical sequence of buffers forming virtual queues in the common memory. Each virtual queue is associated with a port. A memory manager selects buffers of the common memory so as to cause the interface to populate the plurality of virtual queues with data packets.