Mapped Region Table for SSD Trim Bitmap Management

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Solution Overview

Problem

Traditional Trim Bitmaps in non-volatile memory devices, such as SSDs, face challenges with growing size and volatility, leading to difficulties in maintaining accuracy during sudden power loss and increased processing overheads, which can result in the retrieval of previously erased data.

Innovation Solution

Implementing a Mapped Region Table with two bitmaps - a Grouped Trim Bitmap and a Mapped Region Table - to efficiently manage the validity states of logical addresses, allowing for reduced storage size and improved data integrity by determining and modifying validity states, thereby ensuring accurate data deletion and retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional Trim Bitmap is used in volatile memory, then data validity tracking is achieved, but the bitmap size grows with SSD capacity making it impossible to save during sudden power loss

Engineering Contradiction:
Improvedata integrityVSAvoidbitmap size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides the traditional single Trim Bitmap into two separate structures: a Grouped Trim Bitmap that tracks validity at the logical block level, and individual LBA-level bitmaps only when needed. This segmentation allows the main bitmap to remain small and saveable during power loss, while detailed tracking is maintained separately.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the essential validity tracking function from the traditional monolithic Trim Bitmap and implements it through a hybrid system that uses grouped bitmaps at the logical block level, separating the high-level validity information from the detailed LBA-level information to reduce overall storage requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If a traditional Trim Bitmap is used, then validity tracking is maintained, but processing overheads increase during rebuilding after power loss

Engineering Contradiction:
Improvevalidity tracking accuracyVSAvoidrebuilding speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the validity tracking into grouped bitmaps at the logical block level rather than maintaining a complete LBA-level bitmap, the patent reduces the amount of data that needs to be processed during rebuilding operations, thereby improving productivity while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by only maintaining detailed LBA-level bitmaps when necessary (when a logical block is fully invalidated), rather than continuously maintaining complete bitmap information, thus reducing processing overhead during normal operation and rebuilding.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of manufacture

If data is marked as invalid in the Bitmap table, then deletion is achieved, but previously erased data may be returned on subsequent reads

Engineering Contradiction:
Improvedeletion operationVSAvoiddata security
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by maintaining the grouped trim bitmap information even after logical blocks are invalidated, ensuring that the validity state is preserved and can be enforced during subsequent read operations. This prevents previously erased data from being returned by maintaining the invalidation markers in the grouped bitmap structure.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10061708B2Mapped region table
Publication Date: 2018.08.28 SK HYNIX INC
  • US10061708B2 patent drawing
  • US10061708B2 patent drawing
  • US10061708B2 patent drawing

AI summary

Techniques and systems for first determining if a non-volatile memory configured to store physical data pages is being initialized, and a volatile memory configured to store (a) plurality of physical data page addresses, each physical data page address corresponding to a physical data page and accessed via a corresponding logical address (b) first bitmap including plurality of first set of bits with each bit configured to indicate a validity state of a different first plurality of logical addresses, and (c) a second bitmap including a plurality of second set of bits, each bit in second set of bits configured to indicate a validity state of (i) different second plurality of logical addresses, and (ii) different first set of bits in first bitmap; accessing second bitmap based on first determining; and second determining of invalid state of at least one of selected logical address(es) based on a bit in second bitmap.