Mapping Entry Invalidation Tracking Memory Access Completions
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Solution Overview
Problem
In computing systems, premature invalidation of mapping entries in memory address translators can lead to errors due to uncompleted memory access requests, as the second memory access translator may invalidate virtual addresses before all requests have been completed.
Innovation Solution
Implementing a memory access system with a mapping entry invalidator that tracks the completion of memory access requests at the first memory address translator and delays the invalidation of corresponding entries in the second memory address translator until all requests are completed, using a counter to monitor the status of outstanding requests and issuing requests to invalidate only when all have been finished.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the second memory access translator invalidates mapping entries immediately when requested, then the system responds quickly to invalidation requests, but mapping entries may be invalidated before all in-transit memory access requests are completed, causing errors
Solution Approach 1:
The system performs preliminary tracking of in-transit memory access requests before invalidating mapping entries. The second memory access translator monitors and counts outstanding requests, ensuring all are completed before invalidation occurs, thus preventing premature invalidation errors
Solution Approach 2:
The system implements a feedback mechanism where the second memory access translator receives status information about in-transit requests from the first translator and adjusts invalidation timing accordingly. The counter feedback ensures invalidation only occurs when the counter reaches zero, indicating all requests are complete
2Reliability
If the system tracks completion of all memory access requests before invalidation, then mapping entry validity is maintained, but the system complexity increases due to additional tracking mechanisms
Solution Approach 1:
The counter mechanism serves multiple functions: it tracks in-transit requests, signals when tracking is complete, and controls invalidation timing. This multi-functionality reduces the need for separate dedicated components for each function, thereby reducing overall system complexity
Solution Approach 2:
The counter acts as an intermediary between the first and second memory access translators, coordinating the invalidation process without requiring complex direct communication protocols. This simple intermediary mechanism manages the complexity of coordinating between two translators
Data Source
AI summary
A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.