Mapping Portal Bridge for PCI Express BDF Address Translation

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Solution Overview

Problem

Traditional PCI Express systems inefficiently use Bus Numbers in the BDF space, leading to wasted resources and scalability issues, especially in deep hierarchies and applications supporting hot plugging, where rebalancing bus numbers is slow and disruptive to system operations.

Innovation Solution

The implementation of a Mapping Portal Bridge (MPB) that enables efficient translation and remapping of BDF spaces, allowing for compact allocation of bus addresses and reducing the need for dedicated resources in the Root Complex, enabling faster rebalancing of bus numbers without placing PCI Functions in a quiescent state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional PCI Express systems use standard BDF space allocation, then device configuration is straightforward, but bus number utilization is inefficient and scalability is limited

Engineering Contradiction:
ImprovescalabilityVSAvoidwasted bus number resources
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent introduces a Mapping Portal Bridge (MPB) as an intermediary device between the root complex and downstream devices. The MPB maintains translation tables that map primary BDF addresses to secondary BDF addresses, enabling efficient bus number allocation without requiring the root complex to directly manage all address translations. This intermediary structure allows compact allocation of bus addresses and improves scalability while reducing wasted resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If bus numbers are rebalanced in traditional PCI Express systems, then resource allocation can be optimized, but system operations are disrupted and the process is slow

Engineering Contradiction:
Improverebalancing speedVSAvoidsystem disruption
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent implements dynamic bus number rebalancing by allowing the MPB to update translation tables without requiring PCI Functions to enter a quiescent state. The system can dynamically adjust bus number allocations while maintaining operational continuity, enabling faster rebalancing with minimal disruption to system operations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The MPB pre-establishes translation tables that map primary BDF addresses to secondary BDF addresses before rebalancing is needed. When rebalancing becomes necessary, the system can switch to updated translation tables without disrupting ongoing operations, as the translation infrastructure is already in place and can be updated in advance.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If multiple Root Complexes are used to improve scalability, then device connectivity increases, but address space management becomes more complex

Engineering Contradiction:
Improvedevice connectivityVSAvoidaddress space management
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the address space management function by introducing MPBs at strategic points in the hierarchy. Each MPB manages translation for its specific downstream segment, breaking down the complex global address management into smaller, localized translation tasks. This segmentation allows multiple Root Complexes to operate with simplified individual address management while maintaining overall system scalability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10061707B2Speculative enumeration of bus-device-function address space
Publication Date: 2018.08.28 INTEL CORP
  • US10061707B2 patent drawing
  • US10061707B2 patent drawing
  • US10061707B2 patent drawing

AI summary

A first device is determined as connected to a first one of a plurality of ports of a root complex. Addresses are assigned corresponding to a first hierarchy of devices including the first device. A second device is determined as connected through a mapping portal bridge at a second one of the ports of the root complex, the second device included in another second hierarchy of devices. A mapping table is generated that corresponds to the mapping portal bridge. The mapping table defines a translation between addressing used in a first view of a configuration address space of the system and addressing used in a second view of the configuration address space. The first view includes a view of the root complex and the second view includes a view corresponding to the second hierarchy of devices, the first hierarchy of devices being addressed according to the first view.