Mapping Physical Shift Failures to Scan Cells for IC Fault Diagnosis
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Solution Overview
Problem
In integrated circuit fault diagnosis, standard scan testing and compression methods often fail to accurately identify physical faults due to 'X' values and fault aliasing, leading to incorrect identification of failing scan cells and reduced fault coverage.
Innovation Solution
The method involves mapping physical shift failures to specific scan cells using convolutional compactors and logic cone tracing, with fault simulation to identify and score potential faults, ensuring accurate fault localization by distinguishing between correct and incorrect mappings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scan data is compressed using convolutional compactors, then test response compression is achieved, but X values interfere with known values and reduce fault coverage
Solution Approach 1:
The patent segments the test response compression process by introducing separate compression paths for known values and X values through the convolutional compactor. This segmentation allows known values to be preserved with higher reliability while still achieving compression of the overall test data, resolving the contradiction between compression ratio and fault coverage.
Solution Approach 2:
The patent introduces an intermediary mapping process that correlates compacted test responses with original scan cell values. This intermediary layer enables accurate identification of failing scan cells even when compression is applied, maintaining fault coverage while achieving data compression.
2Quantity of substance
If fault aliasing occurs in compressed scan testing, then test response compression is achieved, but identification of failing scan cells becomes incorrect
Solution Approach 1:
The patent implements a feedback mechanism where the mapping process uses the known structure of the convolutional compactor to trace back compacted test responses to their original scan cell sources. This feedback loop corrects potential aliasing errors and ensures accurate identification of failing scan cells despite compression-induced signal mixing.
Solution Approach 2:
The patent performs preliminary mapping of scan cells to their expected compacted positions before actual fault analysis. This preliminary action establishes a reference framework that prevents aliasing misinterpretation during the actual test response analysis, maintaining identification accuracy under compression.
3Adaptability or versatility
If don't care values are present in test response signals, then test flexibility is improved, but fault simulation accuracy decreases due to interference with known values
Solution Approach 1:
The patent applies local quality by treating don't care values differently from known values in the compression process. The convolutional compactor preserves the local integrity of known values while allowing flexible handling of don't care positions, enabling fault simulation to focus on critical signal paths without interference from indeterminate values.
Data Source
AI summary
Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the integrated circuit causing the physical shift failures.